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* target/xtensa: extract unconditional TB termination via slot 0Max Filippov2018-10-011-47/+36Star
| | | | | | | | - mark instructions that require TB termination via slot 0; - put TB termination right after the instruction translation loop, if termination w/o TB linking wasn't requested; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: always end TB on CCOUNT access/CCOMPARE writeMax Filippov2018-10-011-8/+5Star
| | | | | | | | Currently we only end TB in icount mode, because access to CCOUNT or write to CCOMPARE are IO operations. Simplify the behaviour a bit and end TB unconditionally. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: change SR number checks to assertionsMax Filippov2018-10-011-36/+29Star
| | | | | | | | Opcode decoding with libisa takes care about range of valid group SRs, like CCOMPARE, IBREAKA, DBREAKA or DBREAKC. Turn range checks in wsr implementations into assertions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract unconditional TB terminationMax Filippov2018-10-011-39/+28Star
| | | | | | | | - mark all instructions that exit TB and require dynamic search for the next TB; - put TB termination right after the instruction translation loop; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for division by zeroMax Filippov2018-10-011-22/+31
| | | | | | | | | | - mark quos/quou/rems/remu instructions; - drop parameter 0 from the translate_quou and split translate_remu from it; - put test for division by zero exception right after the coprocessor exception test; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for cpdisabled exceptionMax Filippov2018-10-011-108/+122
| | | | | | | | | | | | - add XtensaOpcodeOps::coprocessor with bitmask of coprocessors used by the instruction; - replace coprocessor id parameter of gen_check_cpenable with the bitmask of used coprocessors; - collect coprocessor IDs used by an instruction in the disassembly loop; - put test for coprocessor disabled exception after the alloca test; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for alloca exceptionMax Filippov2018-10-011-3/+8
| | | | | | | | - mark movsp instruction; - put test for alloca exception right after the test for window underflow; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for window underflow exceptionMax Filippov2018-10-011-0/+9
| | | | | | | | | - mark retw and retw.n instructions; - extract window inderflow test from retw helper; - put underflow exception check generation right after the overflow check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for window overflow exceptionMax Filippov2018-10-011-582/+880
| | | | | | | | | | | | | | | | | | | | - add ps.callinc to the TB flags, that allows testing all instructions for window overflow statically; - drop gen_window_check* functions; replace them with get_window_check that accepts bitmask of used registers; - add XtensaOpcodeOps::test_overflow that returns bitmask of implicitly used registers; use it for entry and call{,x}{4,8,12}; - drop window overflow test from the entry helper; - drop parameter 0 from translate_[di]cache and use translate_nop for d/i cache opcodes that don't need memory accessibility check; - add bitmask XtensaOpcodeOps::windowed_register_op that marks opcode arguments that refer to windowed registers; - translate windowed_register_op mask to a mask of actually used registers in the disassembly loop; - add check for window overflow right after the check for debug exception; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for debug exceptionMax Filippov2018-10-011-10/+13
| | | | | | | | | - mark break and break.n instructions; - collect debug cause bits from parameter 0 of instructions marked for debug exception; - put debug exception check right after syscall check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for syscall instructionMax Filippov2018-10-011-7/+6Star
| | | | | | | - mark syscall instruction; - put syscall exception check right after privileged exception check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for privileged instructionMax Filippov2018-10-011-93/+294
| | | | | | | | - mark privileged instructions; - put single privileged instruction check after disassembly loop; - translate_[di]cache: drop parameter 0, shift parameters one down; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract test for an illegal instructionMax Filippov2018-10-011-35/+332
| | | | | | | | | | | - TB flags: add XTENSA_TBFLAG_CWOE that corresponds to the architectural CWOE state; - entry: move CWOE check from the helper to the test_ill_entry; - retw: move CWOE check from the helper to the test_ill_retw; - separate instruction disassembly loop and translation loop; save disassembly results in local array; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov2018-09-171-1/+1
| | | | | | | | | | | s32c1i must load and store value with target endianness, not host. This results in an infinite loop in atomic cmpxchg sequences when target endianness doesn't match host endianness. Fixes: 9fb40342d4b3 ("target/xtensa: support MTTCG") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/xtensa: fix FPU2000 bugsMax Filippov2018-09-171-3/+3
| | | | | | | | | | | - FPU2000 defines rfr and wfr opcodes, not rfr.s and wfr.s; - movcond.s uses incorrect operand in tcg_gen_movcond: in case the condition is not satisfied it must not change its argument 0. Fixes: c04e1692e3aa ("target/xtensa: extract FPU2000 opcode translators") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: Convert to TranslatorOpsRichard Henderson2018-06-301-101/+116
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: Change gen_intermediate_code dc to pointerRichard Henderson2018-06-301-61/+61
| | | | | | | | This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: Convert to DisasContextBaseRichard Henderson2018-06-301-47/+44Star
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURNRichard Henderson2018-06-301-12/+9Star
| | | | | | | | The usage of DISAS_UPDATE is after noreturn helpers. It is thus indistinguishable from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: check zero overhead loop alignmentMax Filippov2018-06-301-0/+7
| | | | | | | | | ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé2018-06-081-3/+3
| | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 20180606152128.449-12-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-2/+2
| | | | | | | | | Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into ↵Peter Maydell2018-05-211-5/+2Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging trivial patches for 2018-05-20 # gpg: Signature made Sun 20 May 2018 07:13:20 BST # gpg: using RSA key 701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * remotes/mjt/tags/trivial-patches-fetch: (22 commits) acpi: fix a comment about aml_call0() qapi/net.json: Fix the version number of the "vlan" removal gdbstub: Handle errors in gdb_accept() gdbstub: Use qemu_set_cloexec() replace functions which are only available in glib-2.24 typedefs: Remove PcGuestInfo from qemu/typedefs.h qemu-options: Allow -no-user-config again hw/timer/mt48t59: Fix bit-rotten NVRAM_PRINTF format strings Remove unnecessary variables for function return value trivial: Do not include pci.h if it is not necessary tests: fix tpm-crb tpm-tis tests race hw/ide/ahci: Keep ALLWINNER_AHCI() macro internal qemu-img-cmds.hx: add passive-aggressive note qemu-img: Make documentation between .texi and .hx consistent qemu-img: remove references to GEN_DOCS qemu-img.texi: fix command ordering qemu-img-commands.hx: argument ordering fixups HACKING: document preference for g_new instead of g_malloc qemu-option-trace: -trace enable= is a pattern, not a file slirp/debug: Print IP addresses in human readable form ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Remove unnecessary variables for function return valueLaurent Vivier2018-05-201-5/+2Star
| | | | | | | | | | | | | | | | | | Re-run Coccinelle script scripts/coccinelle/return_directly.cocci Signed-off-by: Laurent Vivier <lvivier@redhat.com> ppc part Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | target/xtensa: Honor CPU_DUMP_FPURichard Henderson2018-05-181-1/+2
|/ | | | | | Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2018-05-111-17/+33
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension # gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/riscv/translate.c
| * target/xtensa: Use new min/max expandersRichard Henderson2018-05-101-17/+33
| | | | | | | | | | | | | | | | | | The generic expanders replace nearly identical code in the translator. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | target/xtensa: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-091-5/+4Star
|/ | | | | | | | | | | If the PC is in the last page of the address space, next_page_start overflows to 0. Fix it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/xtensa: add linux-user supportMax Filippov2018-03-161-6/+37
| | | | | | | | | | Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: support MTTCGMax Filippov2018-03-131-15/+31
| | | | | | | | - emit TCG barriers for MEMW, EXTW, S32RI and L32AI; - do atomic_cmpxchg_i32 for S32C1I. Cc: Emilio G. Cota <cota@braap.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: mark register windows in the dumpMax Filippov2018-03-131-2/+7
| | | | | | | Add arrows that mark beginning of register windows and position of the current window in the windowed register file. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: dump correct physical registersMax Filippov2018-03-131-0/+1
| | | | | | | | | | xtensa_cpu_dump_state outputs CPU physical registers as is, without synchronization from current window. That may result in different values printed for the current window and corresponding physical registers. Synchronize physical registers from window before dumping. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into stagingPeter Maydell2018-01-241-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | target/xtensa updates: - make mini-bootloader independent of the initial CPU state; - add noMMU XTFPGA variants; - add two noMMU cores: de212 and sample_controller; - fix issues reported by coverity against xtensa translator and disassembler. # gpg: Signature made Mon 22 Jan 2018 20:00:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180122-xtensa: target/xtensa: disas/xtensa: fix coverity warnings target/xtensa: add sample_controller core target/xtensa: allow different default CPU for MMU/noMMU target/xtensa: add de212 core hw/xtensa/xtfpga: support noMMU cores hw/xtensa/xtfpga: extract flash configuration hw/xtensa: extract xtensa_create_memory_regions target/xtensa: fix default sysrom/sysram addresses hw/xtensa/xtfpga: clean up function/structure names hw/xtensa/xtfpga: rewrite mini bootloader Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/xtensa: disas/xtensa: fix coverity warningsMax Filippov2018-01-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | Coverity warnings CID 1385146, 1385148 1385149 and 1385150 point that xtensa_opcode_num_operands and xtensa_format_num_slots may return -1 even when xtensa_opcode_decode and xtensa_format_decode succeed. In that case unsigned counters used to iterate through operands/slots will not do the right thing. Make counters and loop bounds signed to fix the warnings. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* | target/xtensa: Remove duplicate typedef of DisasContextPeter Maydell2018-01-121-2/+2
|/ | | | | | | | | | | | | | Some older versions of gcc complain if a typedef is defined twice: target/xtensa/translate.c:81: error: redefinition of typedef 'DisasContext' target/xtensa/cpu.h:339: note: previous declaration of 'DisasContext' was here Remove the now-redundant typedef from the definition of the struct in translate.c. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1515762528-22818-1-git-send-email-peter.maydell@linaro.org
* target/xtensa: implement const16Max Filippov2018-01-091-0/+14
| | | | | | | | | const16 is an opcode that shifts 16 lower bits of an address register to the 16 upper bits and puts its immediate operand into the lower 16 bits. It is not controlled by an Xtensa option and doesn't have a fixed opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: implement GPIO32Max Filippov2018-01-091-0/+53
| | | | | | | | GPIO32 is not in the core ISA, but it was widely used in Diamond Cores. This implementation doesn't do actual I/O and doesn't handle the case of GPIO32 state being a part of coprocessor. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: implement salt/saltuMax Filippov2018-01-091-0/+18
| | | | | | | SALT/SALTU are recent additions to the core Xtensa ISA that do signed/unsigned setcond. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: add internal/noop SRs and opcodesMax Filippov2018-01-091-0/+33
| | | | | | | | | | | | | | | | | | | Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: drop DisasContext::litbaseMax Filippov2018-01-091-22/+5Star
| | | | | | | It doesn't help much, always-set bit 0 of the LITBASE SR is easy to compensate with decrement of the l32r immediate argument. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: use libisa for instruction decodingMax Filippov2018-01-091-2144/+84Star
| | | | | | | | | Replace manual opcode analysis with libisa-based code. This makes it possible to support variable-encoding instructions of the core ISA, like const16, and will allow to support advanced Xtensa features, like FLIX and TIE. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract FPU2000 opcode translatorsMax Filippov2017-12-191-0/+374
| | | | | | | | | FPU2000 implements basic single-precision floating point operations and can be replaced with a different implementation, like DFPU or HiFi. Move FPU2000 opcode translators into separate functions and list them in a separate array. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: extract core opcode translatorsMax Filippov2017-12-191-0/+3121
| | | | | | | | Move implementations of core opcodes into separate translation functions. Introduce data structures for mapping opcode name to translator function. Make an array of core opcode/translator structures. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: pass actual frame size to the entry helperMax Filippov2017-12-191-1/+1
| | | | | | | | Currently 'entry' opcode helper accepts frame size divided by 8, as it is encoded in the opcode. Make it more natural and accept actual frame size instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-14/+14
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-0/+4
| | | | | | | | | | | Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 14:01:32 +0100