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* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-102-2/+2
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-052-3/+3
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move debug_excp_handler to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* xtensa tcg cpus: Fix Lesser GPL version numberChetan Pant2020-11-151-1/+1
* hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf2020-11-131-1/+1
* target/xtensa: enable all coprocessors for linux-userMax Filippov2020-10-261-0/+1
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-232-3/+3
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-3/+5
* target/xtensa: import DSP3400 coreMax Filippov2020-08-216-0/+173129
* target/xtensa: import de233_fpu coreMax Filippov2020-08-216-0/+22538
* target/xtensa: implement FPU division and square rootMax Filippov2020-08-213-0/+132
* target/xtensa: add DFPU registers and opcodesMax Filippov2020-08-216-34/+1413
* target/xtensa: add DFPU optionMax Filippov2020-08-212-0/+25
* target/xtensa: don't access BR regfile directlyMax Filippov2020-08-213-34/+42
* target/xtensa: move FSR/FCR register accessorsMax Filippov2020-08-211-32/+32
* target/xtensa: rename FPU2000 translators and helpersMax Filippov2020-08-213-55/+57
* target/xtensa: support copying registers up to 64 bits wideMax Filippov2020-08-212-5/+22
* target/xtensa: add geometry to xtensa_get_regfile_by_nameMax Filippov2020-08-213-10/+31
* target/xtensa: implement NMI supportMax Filippov2020-08-213-9/+21
* target/xtensa: make opcode properties more dynamicMax Filippov2020-08-212-265/+278
* meson: targetPaolo Bonzini2020-08-212-16/+30
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-2121-17/+17
* Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into stagingPeter Maydell2020-06-253-23/+46
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| * target/xtensa: drop gen_io_end callMax Filippov2020-06-221-3/+0Star
| * target/xtensa: fix simcall for newer hardwareMax Filippov2020-05-171-3/+6
| * target/xtensa: fetch HW version from configuration overlayMax Filippov2020-05-172-3/+6
| * target/xtensa: work around missing SR definitionsMax Filippov2020-04-301-14/+34
* | softfloat: Name compare relation enumRichard Henderson2020-05-191-3/+3
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* gdbstub: Do not use memset() on GByteArrayPhilippe Mathieu-Daudé2020-04-151-4/+2Star
* target/xtensa: statically allocate xtensa_insnbufs in DisasContextMax Filippov2020-04-083-16/+6Star
* target/xtensa: fix pasto in pfwait.r opcode nameMax Filippov2020-04-081-1/+1
* target/xtensa: add FIXME for translation memory leakAlex Bennée2020-04-071-0/+5
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-192-5/+5
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-182-5/+5
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-172-2/+2
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* cpu: Use cpu_class_set_parent_reset()Greg Kurz2020-01-241-2/+1Star
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIXRichard Henderson2020-01-161-4/+0Star
* target/xtensa: Use probe_access for itlb_hit_testRichard Henderson2020-01-161-2/+3
* target/xtensa: use MPU background map from core configurationMax Filippov2020-01-062-2/+17
* target/xtensa: import xtensa/config/core-isa.hMax Filippov2020-01-061-2/+2
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