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* Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-01-231-0/+1
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| * x86/cpu: Use max host physical address if -cpu max option is appliedYang Weijiang2021-01-211-0/+1
* | s390x: Use strpadcpy for copying vm nameMiroslav Rezanina2021-01-212-9/+10
* | s390x/tcg: Ignore register content if b1/b2 is zero when handling EXECUTEDavid Hildenbrand2021-01-211-2/+2
* | s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x"David Hildenbrand2021-01-212-10/+13
* | s390x/tcg: Fix RISBHGDavid Hildenbrand2021-01-211-10/+8Star
* | s390x/tcg: Fix ALGSIDavid Hildenbrand2021-01-211-1/+1
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized errorPhilippe Mathieu-Daudé2021-01-191-1/+1
* target/arm: Update REV, PUNPK for pred_descRichard Henderson2021-01-192-13/+8Star
* target/arm: Update ZIP, UZP, TRN for pred_descRichard Henderson2021-01-192-17/+13Star
* target/arm: Update PFIRST, PNEXT for pred_descRichard Henderson2021-01-192-6/+7
* target/arm: Introduce PREDDESC field definitionsRichard Henderson2021-01-191-0/+9
* target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont2021-01-191-14/+11Star
* target/arm: enable Secure EL2 in max CPURémi Denis-Courmont2021-01-191-0/+1
* target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont2021-01-194-8/+36
* target/arm: revector to run-time pick target ELRémi Denis-Courmont2021-01-191-2/+21
* target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont2021-01-194-0/+13
* target/arm: secure stage 2 translation regimeRémi Denis-Courmont2021-01-193-25/+81
* target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont2021-01-191-7/+6Star
* target/arm: translate NS bit in page-walksRémi Denis-Courmont2021-01-191-0/+12
* target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont2021-01-191-3/+6
* target/arm: handle VMID change in secure stateRémi Denis-Courmont2021-01-191-4/+9
* target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont2021-01-192-0/+31
* target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont2021-01-195-58/+124
* target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont2021-01-192-7/+7
* target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont2021-01-191-0/+5
* target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont2021-01-191-16/+22
* target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont2021-01-191-13/+18
* target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont2021-01-193-29/+16Star
* target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont2021-01-191-0/+17
* target/arm: remove redundant testsRémi Denis-Courmont2021-01-192-10/+8Star
* target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson2021-01-191-14/+10Star
* target/arm: Add cpu properties to control pauthRichard Henderson2021-01-194-4/+60
* target/arm: Implement an IMPDEF pauth algorithmRichard Henderson2021-01-192-9/+33
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell2021-01-1812-1184/+99Star
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| * riscv: Add semihosting supportKeith Packard2021-01-184-1/+58
| * semihosting: Change common-semi API to be architecture-independentKeith Packard2021-01-183-11/+9Star
| * semihosting: Move ARM semihosting code to shared directoriesKeith Packard2021-01-182-1123/+0Star
| * target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée2021-01-182-47/+30Star
| * gdbstub: drop CPUEnv from gdb_exit()Alex Bennée2021-01-183-3/+3
* | target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-163-264/+58Star
* | target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-162-84/+249
* | target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-162-9/+9
* | target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-163-2/+8
* | gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
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* target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2021-01-142-10/+7Star
* target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2021-01-142-5/+2Star
* target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé2021-01-141-1/+0Star
* target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+2
* target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
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