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* target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2021-12-202-9/+15
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-204-50/+50
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-204-45/+121
* target/riscv: rvv-1.0: slide instructionsFrank Chang2021-12-201-7/+12
* target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2021-12-202-5/+2Star
* target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang2021-12-201-9/+0Star
* target/riscv: rvv-1.0: integer comparison instructionsFrank Chang2021-12-202-11/+2Star
* target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang2021-12-204-51/+51
* target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang2021-12-203-26/+17Star
* target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang2021-12-204-6/+102
* target/riscv: rvv-1.0: integer extension instructionsFrank Chang2021-12-204-0/+133
* target/riscv: rvv-1.0: whole register move instructionsFrank Chang2021-12-202-0/+29
* target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang2021-12-203-26/+21Star
* target/riscv: rvv-1.0: floating-point move instructionFrank Chang2021-12-201-2/+14
* target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang2021-12-202-9/+37
* target/riscv: rvv-1.0: register gather instructionsFrank Chang2021-12-204-12/+43
* target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang2021-12-201-10/+22
* target/riscv: rvv-1.0: element index instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: iota instructionFrank Chang2021-12-202-3/+9
* target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang2021-12-203-8/+7Star
* target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang2021-12-204-7/+7
* target/riscv: rvv-1.0: count population in mask instructionFrank Chang2021-12-204-8/+9
* target/riscv: rvv-1.0: floating-point classify instructionsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: floating-point square-root instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang2021-12-203-13/+42
* target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang2021-12-202-51/+80
* target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang2021-12-204-0/+176
* target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang2021-12-204-109/+38Star
* target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...Frank Chang2021-12-201-4/+4
* target/riscv: rvv-1.0: index load and store instructionsFrank Chang2021-12-204-151/+145Star
* target/riscv: rvv-1.0: stride load and store instructionsFrank Chang2021-12-204-447/+300Star
* target/riscv: rvv-1.0: configure instructionsFrank Chang2021-12-202-36/+40
* target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang2021-12-204-316/+0Star
* target/riscv: rvv:1.0: add translation-time nan-box helper functionFrank Chang2021-12-201-1/+34
* target/riscv: introduce more imm value modes in translator functionsFrank Chang2021-12-201-49/+66
* target/riscv: rvv-1.0: update check functionsFrank Chang2021-12-201-208/+507
* target/riscv: rvv-1.0: add VMA and VTAFrank Chang2021-12-202-1038/+891Star
* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-203-16/+42
* target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang2021-12-204-187/+111Star
* target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang2021-12-201-0/+5
* target/riscv: rvv-1.0: add vlenb registerGreentime Hu2021-12-202-0/+8
* target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei2021-12-202-0/+24
* target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang2021-12-201-13/+0Star
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-204-14/+109
* target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei2021-12-202-1/+2
* target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang2021-12-201-0/+1
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