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* s390x: Beautify diag308 handlingJanosch Frank2019-12-141-22/+32
* s390x: Move clear resetJanosch Frank2019-12-142-41/+18Star
* s390x: Move initial resetJanosch Frank2019-12-144-31/+21Star
* s390x: Move reset normal to shared reset handlerJanosch Frank2019-12-144-9/+20
* target/i386: disable VMX features if nested=0Yang Zhong2019-12-061-0/+8
* hvf: correctly inject VMCS_INTR_T_HWINTR versus VMCS_INTR_T_SWINTR.Cameron Esfahani2019-12-032-6/+12
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2019-11-267-72/+104
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| * hvf: more accurately match SDM when setting CR0 and PDPTE registersCameron Esfahani2019-11-262-8/+18
| * hvf: correctly handle REX prefix in relation to legacy prefixesCameron Esfahani2019-11-262-38/+46
| * hvf: remove TSC synchronization code because it isn't fully completeCameron Esfahani2019-11-263-9/+1Star
| * hvf: non-RAM, non-ROMD memory ranges are now correctly mapped inCameron Esfahani2019-11-261-15/+35
| * target/i386: add two missing VMX features for Skylake and CascadeLake ServerPaolo Bonzini2019-11-261-2/+4
* | target/arm: Honor HCR_EL2.TID3 trapping requirementsMarc Zyngier2019-11-261-0/+76
* | target/arm: Fix ISR_EL1 tracking when executing at EL2Marc Zyngier2019-11-261-2/+5
* | target/arm: Fix handling of cortex-m FTYPE flag in EXCRETJean-Hugues Deschênes2019-11-261-4/+3Star
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* i386: Add -noTSX aliases for hle=off, rtm=off CPU modelsEduardo Habkost2019-11-211-0/+5
* i386: Add new versions of Skylake/Cascadelake/Icelake without TSXEduardo Habkost2019-11-211-0/+47
* target/i386: add support for MSR_IA32_TSX_CTRLPaolo Bonzini2019-11-214-1/+39
* target/i386: add VMX features to named CPU modelsPaolo Bonzini2019-11-211-0/+705
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2019-11-192-4/+4
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| * hw/i386: Move save_tsc_khz from PCMachineClass to X86MachineClassLiam Merwick2019-11-191-2/+2
| * target/i386: Export TAA_NO bit to guestsPawan Gupta2019-11-191-1/+1
| * target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSRPaolo Bonzini2019-11-191-1/+1
* | target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLYRichard Henderson2019-11-192-43/+73
* | target/arm: Relax r13 restriction for ldrex/strex for v8.0Richard Henderson2019-11-191-4/+8
* | target/arm: Do not reject rt == rt2 for strexdRichard Henderson2019-11-191-1/+1
* | target/arm: Merge arm_cpu_vq_map_next_smaller into sole callerRichard Henderson2019-11-193-20/+7Star
* | Merge remote-tracking branch 'remotes/vivier2/tags/ppc-for-4.2-pull-request' ...Peter Maydell2019-11-181-8/+13
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| * spapr/kvm: Set default cpu model for all machine classesDavid Gibson2019-11-181-8/+13
* | target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-144-43/+21Star
* | remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata2019-11-141-3/+1Star
* | target/microblaze: Plug temp leak around eval_cond_jmp()Edgar E. Iglesias2019-11-121-1/+4
* | target/microblaze: Plug temp leaks with delay slot setupEdgar E. Iglesias2019-11-121-12/+14
* | target/microblaze: Plug temp leaks for loads/storesEdgar E. Iglesias2019-11-121-26/+20Star
* | target/sparc: Define an enumeration for accessing env->regwptrRichard Henderson2019-11-061-0/+33
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* target/arm: Allow reading flags from FPSCR for M-profileChristophe Lyon2019-11-011-2/+3
* target/arm/kvm: host cpu: Add support for sve<N> propertiesAndrew Jones2019-11-014-17/+35
* target/arm/cpu64: max cpu: Support sve properties with KVMAndrew Jones2019-11-013-42/+242
* target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init featuresAndrew Jones2019-11-013-7/+25
* target/arm/kvm64: max cpu: Enable SVE when availableAndrew Jones2019-11-014-4/+65
* target/arm/kvm64: Add kvm_arch_get/put_sveAndrew Jones2019-11-011-28/+155
* target/arm/cpu64: max cpu: Introduce sve<N> propertiesAndrew Jones2019-11-015-2/+250
* target/arm: Allow SVE to be disabled via a CPU propertyAndrew Jones2019-11-013-9/+48
* target/arm/monitor: Introduce qmp_query_cpu_model_expansionAndrew Jones2019-11-011-0/+146
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...Peter Maydell2019-10-3011-32/+21Star
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| * target/openrisc: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
| * target/xtensa: fetch code with translator_ldEmilio G. Cota2019-10-281-2/+2
| * target/sparc: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
| * target/riscv: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
| * target/alpha: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
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