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* target-arm: Add support for Fujitsu A64FXShuuichirou Ishii2021-09-011-0/+48
| | | | | | | | | | | | | | | | | Add a definition for the Fujitsu A64FX processor. The A64FX processor does not implement the AArch32 Execution state, so there are no associated AArch32 Identification registers. For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths. The Identification register values are defined based on the FX700, and have been tested and confirmed. Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable MVE in Cortex-M55Peter Maydell2021-09-011-5/+2Star
| | | | | | | | | We now have a complete MVE emulation, so we can enable it in our Cortex-M55 model by setting the ID registers to match those of a Cortex-M55 with full MVE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE VRINT insnsPeter Maydell2021-09-014-0/+93
| | | | | | | | Implement the MVE VRINT insns, which round floating point inputs to integer values, leaving them in floating point format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE VCVT between single and half precisionPeter Maydell2021-09-014-0/+108
| | | | | | | | Implement the MVE VCVT instruction which converts between single and half precision floating point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE VCVT with specified rounding modePeter Maydell2021-09-014-0/+105
| | | | | | | | | | Implement the MVE VCVT which converts from floating-point to integer using a rounding mode specified by the instruction. We implement this similarly to the Neon equivalents, by passing the required rounding mode as an extra integer parameter to the helper functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE VCVT between fp and integerPeter Maydell2021-09-012-0/+39
| | | | | | | Implement the MVE "VCVT (between floating-point and integer)" insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE VCVT between floating and fixed pointPeter Maydell2021-09-014-0/+82
| | | | | | | | | Implement the MVE VCVT insns which convert between floating and fixed point. As with the Neon equivalents, these use essentially the same constant encoding as right-shift-by-immediate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE fp scalar comparisonsPeter Maydell2021-09-014-24/+131
| | | | | | | Implement the MVE fp scalar comparisons VCMP and VPT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE fp vector comparisonsPeter Maydell2021-09-014-6/+137
| | | | | | | Implement the MVE fp vector comparisons VCMP and VPT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE FP max/min across vectorPeter Maydell2021-09-014-6/+102
| | | | | | | | | | | | | | | | | | | | Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These calculate the maximum or minimum of floating point elements across a vector, starting with a value in a general purpose register and returning the result there. The pseudocode silences a possible SNaN in the accumulating result on every iteration (by calling FPConvertNaN), but we do it only on the input ra, because if none of the inputs to float*_maxnum or float*_minnum are SNaNs then the result can't be an SNaN. Note that we can't use the float*_maxnuma() etc functions we defined earlier for VMAXNMA and VMINNMA, because we mustn't take the absolute value of the starting general-purpose register value, which could be negative. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell2021-09-014-3/+56
| | | | | | | Implement the MVE fp-with-scalar VFMA and VFMAS insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE scalar fp insnsPeter Maydell2021-09-014-6/+85
| | | | | | | Implement the MVE scalar floating point insns VADD, VSUB and VMUL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell2021-09-014-0/+42
| | | | | | | | | | | | | | | | Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but the destination register must be the same as one of the source registers. We defer the decode of the size in bit 28 to the individual insn patterns rather than doing it in the format, because otherwise we would have a single insn pattern that overlapped with two groups (eg VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn patterns per insn seems clearer than a complex multilevel nesting of overlapping and non-overlapping groups. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement MVE VCMUL and VCMLAPeter Maydell2021-09-014-8/+139
| | | | | | | Implement the MVE VCMUL and VCMLA insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement MVE VFMA and VFMSPeter Maydell2021-09-014-0/+48
| | | | | | | Implement the MVE VFMA and VFMS insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement MVE VCADDPeter Maydell2021-09-014-1/+57
| | | | | | | | | | | | Implement the MVE VCADD insn. Note that here the size bit is the opposite sense to the other 2-operand fp insns. We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case, because that would mean we can't use the DO_2OP_FP macro in translate-mve.c. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell2021-09-014-0/+42
| | | | | | | Implement more simple 2-operand floating point MVE insns. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement MVE VADD (floating-point)Peter Maydell2021-09-016-6/+76
| | | | | | | | | | Implement the MVE VADD (floating-point) insn. Handling of this is similar to the 2-operand integer insns, except that we must take care to only update the floating point exception status if the least significant bit of the predicate mask for each element is active. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-012-61/+26Star
| | | | | | | | | Remove gen_get_gpr, as the function becomes unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-25-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-012-210/+57Star
| | | | | | | | | | | | Exit early if check_access fails. Split out do_hlv, do_hsv, do_hlvx subroutines. Use dest_gpr, get_gpr in the new subroutines. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-24-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60Star
| | | | | | | | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-23-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use {get,dest}_gpr for RVFRichard Henderson2021-09-011-76/+70Star
| | | | | | | | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-22-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6Star
| | | | | | | | | | Always use tcg_gen_deposit_z_tl; the special case for shamt >= 32 is handled there. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-21-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19Star
| | | | | | | | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-20-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-013-66/+132
| | | | | | | | | | | | | | | | | | | Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Fix hgeie, hgeipRichard Henderson2021-09-011-18/+8Star
| | | | | | | | | | | | We failed to write into *val for these read functions; replace them with read_zero. Only warn about unsupported non-zero value when writing a non-zero value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-18-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson2021-09-011-8/+15
| | | | | | | | | | We distinguish write-only by passing ret_value as NULL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-17-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
| | | | | | | | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10Star
| | | | | | | | | | Narrow the scope of t0 in trans_jalr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
| | | | | | | | | | These operations can be done in one instruction on some hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-013-202/+125Star
| | | | | | | | | | | | These operations are greatly simplified by ctx->w, which allows us to fold gen_shiftw into gen_shift. Split gen_shifti into gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-012-23/+15Star
| | | | | | | | | | Use ctx->w for ctpopw, which is the only one that can re-use the generic algorithm for the narrow operation. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-012-233/+234
| | | | | | | | | | | | Move these helpers near their use by the trans_* functions within insn_trans/trans_rvb.c.inc. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-012-127/+127
| | | | | | | | | | | | Move these helpers near their use by the trans_* functions within insn_trans/trans_rvm.c.inc. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use gen_arith for mulh and mulhuRichard Henderson2021-09-011-22/+18Star
| | | | | | | | | | Split out gen_mulh and gen_mulhu and use the common helper. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-012-50/+8Star
| | | | | | | | | | Use ctx->w and the enhanced gen_arith function. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-014-90/+64Star
| | | | | | | | | | | | | | Most arithmetic does not require extending the inputs. Exceptions include division, comparison and minmax. Begin using ctx->w, which allows elimination of gen_addw, gen_subw, gen_mulw. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-7-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Introduce DisasExtend and new helpersRichard Henderson2021-09-011-16/+81
| | | | | | | | | | | | | | Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force tcg globals into temps, returning a constant 0 for $zero as source and a new temp for $zero as destination. Introduce ctx->w for simplifying word operations, such as addw. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-019-144/+144
| | | | | | | | | | | We will require the context to handle RV64 word operations. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Clean up division helpersRichard Henderson2021-09-011-83/+91
| | | | | | | | | | | | | | Utilize the condition in the movcond more; this allows some of the setcond that were feeding into movcond to be removed. Do not write into source1 and source2. Re-name "condN" to "tempN" and use the temporaries for more than holding conditions. Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Use tcg_constant_*Richard Henderson2021-09-013-70/+34Star
| | | | | | | | | | | Replace uses of tcg_const_* with the allocate and free close together. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-2-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Add User CSRs read-only checkLIU Zhiwei2021-09-011-3/+5
| | | | | | | | | For U-mode CSRs, read-only check is also needed. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Don't wrongly override isa versionLIU Zhiwei2021-09-011-6/+8
| | | | | | | | | | | For some cpu, the isa version has already been set in cpu init function. Thus only override the isa version when isa version is not set, or users set different isa version explicitly by cpu parameters. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: Correct a comment in riscv_csrrw()Bin Meng2021-09-011-1/+1
| | | | | | | | | | When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned, not -1 (RISCV_EXCP_NONE). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827' ↵Peter Maydell2021-08-2713-1680/+1710
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ppc patch queue 2021-08-27 First ppc pull request for qemu-6.2. As usual, there's a fair bit here, since it's been queued during the 6.1 freeze. Highlights are: * Some fixes for 128 bit arithmetic and some vector opcodes that use them * Significant improvements to the powernv to support POWER10 cpus (more to come though) * Several cleanups to the ppc softmmu code * A few other assorted fixes # gpg: Signature made Fri 27 Aug 2021 08:09:12 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.2-20210827: target/ppc: fix vector registers access in gdbstub for little-endian include/qemu/int128.h: introduce bswap128s target/ppc: fix vextu[bhw][lr]x helpers include/qemu/int128.h: define struct Int128 according to the host endianness ppc/xive: Export xive_presenter_notify() ppc/xive: Export PQ get/set routines ppc/pnv: add a chip topology index for POWER10 ppc/pnv: Distribute RAM among the chips ppc/pnv: Use a simple incrementing index for the chip-id ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode ppc/pnv: Change the POWER10 machine to support DD2 only ppc: Add a POWER10 DD2 CPU ppc/pnv: update skiboot to commit 820d43c0a775. target/ppc: moved store_40x_sler to helper_regs.c target/ppc: moved ppc_store_sdr1 to mmu_common.c target/ppc: divided mmu_helper.c in 2 files spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree xive: Remove extra '0x' prefix in trace events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/ppc: fix vector registers access in gdbstub for little-endianMatheus Ferst2021-08-271-25/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | As vector registers are stored in host endianness, we shouldn't swap its 64-bit elements in user mode. Add a 16-byte case in ppc_maybe_bswap_register to handle the reordering of elements in softmmu and remove avr_need_swap which is now unused. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826145656.2507213-3-matheus.ferst@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * target/ppc: fix vextu[bhw][lr]x helpersMatheus Ferst2021-08-271-28/+10Star
| | | | | | | | | | | | | | | | | | | | | | | | These helpers shouldn't depend on the host endianness, as they only use shifts, ands, and int128_* methods. Fixes: 60caf2216bf0 ("target-ppc: add vextu[bhw][lr]x instructions") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826141446.2488609-3-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering ↵Cédric Le Goater2021-08-271-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | power-saving mode The Hypervisor Decrementer exception should not be generated while the CPU is in power-saving mode (see cpu_ppc_hdecr_excp()). However, discarding the exception before entering the power-saving mode is wrong since we would loose a previously generated HDEC. Fixes: 4b236b621bf0 ("ppc: Initial HDEC support") Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc: Add a POWER10 DD2 CPUCédric Le Goater2021-08-273-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have HAIL but since it does not break the modeling and that we don't plan to support DD1, modify the LPCR mask of all the POWER10 family. Setting the HAIL bit is a requirement to support the scv instruction on PowerNV POWER10 platforms since glibc-2.33. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * target/ppc: moved store_40x_sler to helper_regs.cLucas Mateus Castro (alqotel)2021-08-272-10/+12
| | | | | | | | | | | | | | | | | | | | | | moved store_40x_sler from mmu_common.c to helper_regs.c as it is a function to store a value in a special purpose register, so moving it to a file focused in special register manipulation is more appropriate. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20210723175627.72847-4-lucas.araujo@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-27 14:55:16 +0100