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* target/mips: Fix FTRUNC_S and FTRUNC_U trans helperNi Hui2022-06-111-2/+2
* target/mips: Fix store adress of high 64bit in helper_msa_st_b()Ni Hui2022-06-111-1/+1
* target/mips: Do not treat msa INSERT as NOP when wd is zeroNi Hui2022-06-111-5/+10
* target/mips: Fix msa checking condition in trans_msa_elm_fn()Ni Hui2022-06-111-1/+1
* target/mips: Fix df_extract_val() and df_extract_df() dfe lookupNi Hui2022-06-111-3/+3
* target/mips: Fix SAT_S trans helperNi Hui2022-06-111-1/+1
* target/mips: Fix WatchHi.M handlingMarcin Nowakowski2022-06-113-2/+4
* target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]Richard Henderson2022-06-102-0/+9
* target/arm: Adjust format test in scr_writeRichard Henderson2022-06-101-6/+8
* target/arm: Fix Secure PL1 tests in fp_exception_elRichard Henderson2022-06-101-14/+9Star
* target/arm: Move arm_debug_target_el to debug_helper.cRichard Henderson2022-06-102-21/+21
* target/arm: Create raise_exception_debugRichard Henderson2022-06-101-20/+24
* target/arm: Remove default_exception_elRichard Henderson2022-06-103-26/+0Star
* target/arm: Introduce helper_exception_with_syndromeRichard Henderson2022-06-103-5/+24
* target/arm: Introduce gen_exception_el_vRichard Henderson2022-06-101-5/+8
* target/arm: Introduce gen_exceptionRichard Henderson2022-06-101-4/+7
* target/arm: Rename gen_exception to gen_exception_elRichard Henderson2022-06-101-9/+9
* target/arm: Move gen_exception to translate.cRichard Henderson2022-06-102-8/+7Star
* target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_ELRichard Henderson2022-06-105-18/+4Star
* target/arm: Create helper_exception_swstepRichard Henderson2022-06-103-9/+20
* target/arm: Introduce gen_exception_insnRichard Henderson2022-06-105-29/+22Star
* target/arm: Rename gen_exception_insn to gen_exception_insn_elRichard Henderson2022-06-106-52/+53
* target/arm: Introduce gen_exception_insn_el_vRichard Henderson2022-06-101-15/+12Star
* target/arm: Rename helper_exception_with_syndromeRichard Henderson2022-06-104-10/+10
* target/arm: Move arm_debug_exception_fsr to debug_helper.cRichard Henderson2022-06-102-25/+26
* target/arm: Move exception_bkpt_insn to debug_helper.cRichard Henderson2022-06-102-29/+31
* target/arm: Use is_a64 in arm_generate_debug_exceptionsRichard Henderson2022-06-101-1/+1
* target/arm: Move arm_generate_debug_exceptions out of lineRichard Henderson2022-06-103-91/+95
* target/arm: Move arm_singlestep_active out of lineRichard Henderson2022-06-103-10/+13
* target/arm: Move exception_target_el out of lineRichard Henderson2022-06-102-15/+16
* target/arm: Add coproc parameter to syn_fp_access_trapRichard Henderson2022-06-103-6/+18
* target/arm: Mark exception helpers as noreturnRichard Henderson2022-06-101-3/+3
* target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis2022-06-101-2/+10
* target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis2022-06-101-11/+46
* target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD2022-06-101-0/+2
* target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD2022-06-102-2/+45
* target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD2022-06-102-0/+36
* target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD2022-06-101-0/+20
* target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD2022-06-102-196/+261
* target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...eopXD2022-06-101-106/+114
* target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD2022-06-102-4/+28
* target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD2022-06-101-0/+18
* target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD2022-06-102-1/+13
* target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD2022-06-103-142/+190
* target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD2022-06-103-0/+68
* target/riscv: rvv: Add tail agnostic for vv instructionseopXD2022-06-106-132/+178
* target/riscv: rvv: Early exit when vstart >= vleopXD2022-06-101-0/+27
* target/riscv: rvv: Rename ambiguous eszeopXD2022-06-101-38/+38
* target/riscv: rvv: Prune redundant access_type parameter passedeopXD2022-06-101-19/+16Star
* target/riscv: rvv: Prune redundant ESZ, DSZ parameter passedeopXD2022-06-101-567/+565Star
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