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* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell2021-05-1229-759/+1096
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| * target/riscv: Fix the RV64H decode commentAlistair Francis2021-05-111-1/+1
| * target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-115-72/+39Star
| * target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-1114-150/+166
| * target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis2021-05-111-6/+0Star
| * target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis2021-05-111-6/+0Star
| * target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-114-28/+56
| * target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-113-14/+27
| * target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-112-20/+15Star
| * target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-112-7/+8
| * target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-112-7/+5Star
| * target/riscv: fix a typo with interrupt namesEmmanuel Blot2021-05-111-1/+1
| * target/riscv: fix exception index on instruction access faultEmmanuel Blot2021-05-111-1/+3
| * target/riscv: fix vrgather macro index variable type bugFrank Chang2021-05-111-2/+4
| * target/riscv: Add ePMP support for the Ibex CPUAlistair Francis2021-05-111-0/+1
| * target/riscv/pmp: Remove outdated commentAlistair Francis2021-05-111-4/+0Star
| * target/riscv: Add a config option for ePMPHou Weiying2021-05-112-0/+11
| * target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying2021-05-111-8/+146
| * target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-115-0/+76
| * target/riscv: Add the ePMP featureAlistair Francis2021-05-111-0/+1
| * target/riscv: Define ePMP mseccfgHou Weiying2021-05-111-0/+3
| * target/riscv: Fix the PMP is locked check when using TORAlistair Francis2021-05-111-10/+16
| * target/riscv: Fixup saturate subtract functionLIU Zhiwei2021-05-111-4/+4
| * riscv: don't look at SUM when accessing memory from a debugger contextJade Fink2021-05-111-8/+12
| * target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-114-36/+38
| * target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-112-261/+382
| * target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis2021-05-111-1/+5
| * target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-112-37/+46
| * target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-113-24/+26
| * target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-112-0/+2
| * target/riscv: Align the data type of reset vector addressDylan Jhong2021-05-111-1/+1
| * target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-117-72/+23Star
* | target/i386: use mmu_translate for NPT walkPaolo Bonzini2021-05-111-207/+36Star
* | target/i386: allow customizing the next phase of the translationPaolo Bonzini2021-05-111-12/+18
* | target/i386: extend pg_mode to more CR0 and CR4 bitsPaolo Bonzini2021-05-113-16/+39
* | target/i386: pass cr3 to mmu_translatePaolo Bonzini2021-05-111-6/+6
* | target/i386: extract mmu_translatePaolo Bonzini2021-05-111-65/+86
* | target/i386: move paging mode constants from SVM to cpu.hPaolo Bonzini2021-05-114-21/+31
* | target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constantsPaolo Bonzini2021-05-112-10/+5Star
* | accel: add init_accel_cpu for adapting accel behavior to CPU typeClaudio Fontana2021-05-101-1/+7
* | i386: make cpu_load_efer sysemu-onlyClaudio Fontana2021-05-102-15/+18
* | target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemuClaudio Fontana2021-05-101-0/+10
* | target/i386: gdbstub: introduce aux functions to read/write CS64 regsClaudio Fontana2021-05-101-104/+51Star
* | i386: split off sysemu part of cpu.cClaudio Fontana2021-05-104-379/+429
* | i386: split seg_helper into user-only and sysemu partsClaudio Fontana2021-05-107-229/+311
* | i386: split svm_helper into sysemu and stub-only userClaudio Fontana2021-05-105-61/+80
* | i386: separate fpu_helper sysemu-only partsClaudio Fontana2021-05-104-39/+63
* | i386: split misc helper user stubs and sysemu partClaudio Fontana2021-05-105-467/+519
* | i386: move TCG bpt_helper into sysemu/Claudio Fontana2021-05-106-277/+311
* | i386: split tcg excp_helper into sysemu and user partsClaudio Fontana2021-05-105-573/+623
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