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| * target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis2020-02-271-0/+3
| * target/riscv: Add virtual register swapping functionAlistair Francis2020-02-273-0/+79
| * target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis2020-02-271-0/+27
| * target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis2020-02-271-0/+116
| * target/riscv: Add Hypervisor CSR access functionsAlistair Francis2020-02-271-2/+134
| * target/riscv: Dump Hypervisor registers if enabledAlistair Francis2020-02-271-0/+33
| * target/riscv: Print priv and virt in disas logAlistair Francis2020-02-271-0/+8
| * target/riscv: Fix CSR perm checking for HS modeAlistair Francis2020-02-271-4/+14
| * target/riscv: Add the force HS exception modeAlistair Francis2020-02-273-0/+26
| * target/riscv: Add the virtulisation modeAlistair Francis2020-02-273-0/+25
| * target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-272-9/+9
| * target/riscv: Add support for the new execption numbersAlistair Francis2020-02-274-20/+37
| * target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis2020-02-273-18/+48
| * target/riscv: Add the Hypervisor extensionAlistair Francis2020-02-271-0/+1
| * target/riscv: Convert MIP CSR to target_ulongAlistair Francis2020-02-272-2/+2
* | target/arm: Implement ARMv8.3-CCIDXPeter Maydell2020-02-282-1/+35
* | target/arm: Implement v8.4-RCPCPeter Maydell2020-02-283-1/+96
* | target/arm: Implement v8.3-RCPCPeter Maydell2020-02-283-0/+30
* | target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0Peter Maydell2020-02-281-2/+2
* | target/arm: Split VMINMAXNM decodeRichard Henderson2020-02-282-77/+44Star
* | target/arm: Split VFM decodeRichard Henderson2020-02-282-14/+55
* | target/arm: Add formats for some vfp 2 and 3-register insnsRichard Henderson2020-02-281-90/+60Star
* | target/arm: Remove ARM_FEATURE_VFP*Richard Henderson2020-02-285-37/+0Star
* | target/arm: Move the vfp decodetree calls next to the base isaRichard Henderson2020-02-281-54/+29Star
* | target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson2020-02-283-44/+50
* | target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insnRichard Henderson2020-02-281-4/+0Star
* | target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson2020-02-284-6/+36
* | target/arm: Add missing checks for fpsp_v2Richard Henderson2020-02-281-9/+69
* | target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3Richard Henderson2020-02-281-16/+8Star
* | target/arm: Perform fpdp_v2 check firstRichard Henderson2020-02-281-69/+71
* | target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfpRichard Henderson2020-02-283-5/+20
* | target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}Richard Henderson2020-02-281-0/+18
* | target/arm: Rename isar_feature_aa32_fpdp_v2Richard Henderson2020-02-282-22/+22
* | target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson2020-02-285-14/+25
* | target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfnRichard Henderson2020-02-281-0/+1
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200227' into stagingPeter Maydell2020-02-277-17/+64
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| * s390x: Rename and use constants for short PSW address and maskJanosch Frank2020-02-272-3/+4
| * s390/sclp: improve special wait psw logicChristian Borntraeger2020-02-261-1/+1
| * s390x: Add missing vcpu reset functionsJanosch Frank2020-02-264-12/+58
| * target/s390x/translate: Fix RNSBG instructionThomas Huth2020-02-261-1/+1
* | target/riscv: progressively load the instruction during decodeAlex Bennée2020-02-252-23/+25
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* Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEADPaolo Bonzini2020-02-257-19/+18Star
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| * Avoid cpu_physical_memory_rw() with a constant is_write argumentPhilippe Mathieu-Daudé2020-02-201-2/+2
| * Let cpu_[physical]_memory() calls pass a boolean 'is_write' argumentPhilippe Mathieu-Daudé2020-02-203-6/+6
| * Avoid address_space_rw() with a constant is_write argumentPeter Maydell2020-02-202-10/+9Star
| * Let address_space_rw() calls pass a boolean 'is_write' argumentPhilippe Mathieu-Daudé2020-02-202-5/+5
| * Remove unnecessary cast when using the cpu_[physical]_memory APIPhilippe Mathieu-Daudé2020-02-201-3/+3
| * Remove unnecessary cast when using the address_space APIPhilippe Mathieu-Daudé2020-02-204-4/+4
* | target/i386: check for empty register in FXAMPaolo Bonzini2020-02-251-1/+5
* | target/arm: Set MVFR0.FPSP for ARMv5 cpusRichard Henderson2020-02-211-4/+6