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* kvm: add kvm_arm_get_max_vm_ipa_sizeEric Auger2019-03-052-0/+23
* target/arm: Implement ARMv8.5-FRINTRichard Henderson2019-03-055-5/+173
* target/arm: Restructure handle_fp_1src_{single, double}Richard Henderson2019-03-051-41/+49
* target/arm: Implement ARMv8.5-CondMRichard Henderson2019-03-053-1/+64
* target/arm: Implement ARMv8.4-CondMRichard Henderson2019-03-053-1/+104
* target/arm: Rearrange disas_data_proc_regRichard Henderson2019-03-051-41/+57
* target/arm: Add set/clear_pstate_bits, share gen_ss_advanceRichard Henderson2019-03-055-29/+34
* target/arm: Split helper_msr_i_pstate into 3Richard Henderson2019-03-056-56/+70
* target/arm: Implement ARMv8.0-PredInvRichard Henderson2019-03-054-1/+70
* target/arm: Implement ARMv8.0-SBRichard Henderson2019-03-055-0/+49
* target/arm: Split out arm_sctlrRichard Henderson2019-03-052-15/+17
* target/arm: Fix PC test for LDM (exception return)Richard Henderson2019-03-051-1/+1
* s390x: Add floating-point extension facility to "qemu" cpu modelDavid Hildenbrand2019-03-041-0/+5
* s390x/tcg: Handle all rounding modes overwritten by BFP instructionsDavid Hildenbrand2019-03-041-2/+11
* s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDEDDavid Hildenbrand2019-03-044-15/+44
* s390x/tcg: Implement XxC and checks for most FP instructionsDavid Hildenbrand2019-03-042-126/+247
* s390x/tcg: Prepare for IEEE-inexact-exception control (XxC)David Hildenbrand2019-03-041-57/+57
* s390x/tcg: Refactor saving/restoring the bfp rounding modeDavid Hildenbrand2019-03-042-43/+71
* s390x/tcg: Check for exceptions in SET BFP ROUNDING MODEDavid Hildenbrand2019-03-044-35/+39
* s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modesDavid Hildenbrand2019-03-042-5/+19
* s390x/tcg: Fix simulated-IEEE exceptionsDavid Hildenbrand2019-03-041-0/+13
* s390x/tcg: Refactor SET FPC AND SIGNAL handlingDavid Hildenbrand2019-03-041-10/+12
* s390x/tcg: Hide IEEE underflows in some scenariosDavid Hildenbrand2019-03-041-0/+13
* s390x/tcg: Fix parts of IEEE exception handlingDavid Hildenbrand2019-03-041-6/+32
* s390x/tcg: Factor out conversion of softfloat exceptionsDavid Hildenbrand2019-03-042-12/+20
* s390x/tcg: Fix rounding from float128 to uint64_t/uint32_tDavid Hildenbrand2019-03-041-6/+2Star
* s390x/tcg: Fix TEST DATA CLASS instructionsDavid Hildenbrand2019-03-041-50/+35Star
* s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARYDavid Hildenbrand2019-03-045-0/+31
* s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFPDavid Hildenbrand2019-03-042-0/+8
* s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()David Hildenbrand2019-03-041-15/+26
* s390x/tcg: Factor out vec_full_reg_offset()David Hildenbrand2019-03-041-2/+7
* s390x/tcg: Clarify terminology in vec_reg_offset()David Hildenbrand2019-03-041-5/+6
* s390x/tcg: Simplify disassembler operands initializationDavid Hildenbrand2019-03-041-7/+1Star
* s390x/tcg: RXE has an optional M3 fieldDavid Hildenbrand2019-03-041-1/+1
* s390x/tcg: Save vregs to extended mchk save areaDavid Hildenbrand2019-03-042-3/+47
* s390x: use a QEMU-style typedef + name for SIGP save area structDavid Hildenbrand2019-03-041-4/+4
* s390x: Use cpu_to_be64 in SIGP STORE ADDITIONAL STATUSDavid Hildenbrand2019-03-041-10/+21
* Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into stagingPeter Maydell2019-02-288-1745/+1855
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| * target/xtensa: implement PREFCTL SRMax Filippov2019-02-282-0/+17
| * target/xtensa: prioritize load/store in FLIX bundlesMax Filippov2019-02-282-5/+36
| * target/xtensa: break circular register dependenciesMax Filippov2019-02-281-4/+123
| * target/xtensa: reorganize access to boolean registersMax Filippov2019-02-281-8/+42
| * target/xtensa: reorganize access to MAC16 registersMax Filippov2019-02-281-94/+92Star
| * target/xtensa: reorganize register handling in translatorsMax Filippov2019-02-283-344/+386
| * target/xtensa: only rotate window in the retw helperMax Filippov2019-02-283-9/+10
| * target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov2019-02-284-20/+28
| * target/xtensa: add generic instruction post-processingMax Filippov2019-02-282-8/+33
| * target/xtensa: sort FLIX instruction opcodesMax Filippov2019-02-282-8/+221
| * target/xtensa: implement wide branches and loopsMax Filippov2019-02-191-27/+102
| * target/xtensa: allow multiple names for single opcodeMax Filippov2019-02-193-60/+60
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