| Commit message (Expand) | Author | Age | Files | Lines |
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| * | target/mips: Add disassembler support for nanoMIPS | Aleksandar Markovic | 2018-10-25 | 1 | -2/+11 |
| * | target/mips: Implement emulation of nanoMIPS EVA instructions | Dimitrije Nikolic | 2018-10-25 | 1 | -0/+128 |
| * | target/mips: Add nanoMIPS CRC32 instruction pool | Aleksandar Markovic | 2018-10-25 | 1 | -0/+10 |
| * | Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' in... | Peter Maydell | 2018-10-25 | 6 | -362/+420 |
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| | * | RISC-V: Update CSR and interrupt definitions | Michael Clark | 2018-10-17 | 3 | -321/+370 |
| | * | RISC-V: Move non-ops from op_helper to cpu_helper | Michael Clark | 2018-10-17 | 3 | -36/+35 |
| | * | RISC-V: Allow setting and clearing multiple irqs | Michael Clark | 2018-10-17 | 2 | -18/+28 |
| * | | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part... | Peter Maydell | 2018-10-24 | 3 | -19/+908 |
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| | * | | target/mips: Fix decoding of ALIGN and DALIGN instructions | Aleksandar Markovic | 2018-10-24 | 1 | -8/+32 |
| | * | | target/mips: Fix the title of translate.c | Aleksandar Markovic | 2018-10-24 | 1 | -1/+1 |
| | * | | target/mips: Define the R5900 CPU | Fredrik Noring | 2018-10-24 | 1 | -0/+59 |
| | * | | target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only | Fredrik Noring | 2018-10-24 | 1 | -1/+22 |
| | * | | target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV | Fredrik Noring | 2018-10-24 | 1 | -2/+3 |
| | * | | target/mips: Support R5900 DIV1 and DIVU1 instructions | Fredrik Noring | 2018-10-24 | 1 | -3/+9 |
| | * | | target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions | Fredrik Noring | 2018-10-24 | 1 | -6/+17 |
| | * | | target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions | Fredrik Noring | 2018-10-24 | 1 | -3/+14 |
| | * | | target/mips: Support R5900 three-operand MULT and MULTU instructions | Fredrik Noring | 2018-10-24 | 1 | -0/+74 |
| | * | | target/mips: Add a placeholder for R5900 MMI3 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+30 |
| | * | | target/mips: Add a placeholder for R5900 MMI2 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+39 |
| | * | | target/mips: Add a placeholder for R5900 MMI1 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+35 |
| | * | | target/mips: Add a placeholder for R5900 MMI0 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+42 |
| | * | | target/mips: Add a placeholder for R5900 MMI instruction class | Fredrik Noring | 2018-10-24 | 1 | -1/+44 |
| | * | | target/mips: Add a placeholder for R5900 LQ | Fredrik Noring | 2018-10-24 | 1 | -2/+11 |
| | * | | target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR | Fredrik Noring | 2018-10-24 | 1 | -1/+52 |
| | * | | target/mips: Define R5900 MMI3 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+39 |
| | * | | target/mips: Define R5900 MMI2 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+48 |
| | * | | target/mips: Define R5900 MMI1 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+44 |
| | * | | target/mips: Define R5900 MMI0 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+51 |
| | * | | target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+51 |
| | * | | target/mips: Define R5900 MMI class, and LQ and SQ opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+40 |
| | * | | target/mips: Add R5900 Multimedia Instruction overview note | Fredrik Noring | 2018-10-24 | 1 | -0/+161 |
| | * | | target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants | Fredrik Noring | 2018-10-24 | 1 | -0/+3 |
| * | | | target/arm: Only flush tlb if ASID changes | Richard Henderson | 2018-10-24 | 1 | -5/+3 |
| * | | | target/arm: Remove writefn from TTBR0_EL3 | Richard Henderson | 2018-10-24 | 1 | -1/+1 |
| * | | | target/arm: Reorg NEON VLD/VST single element to one lane | Richard Henderson | 2018-10-24 | 1 | -42/+50 |
| * | | | target/arm: Promote consecutive memory ops for aa32 | Richard Henderson | 2018-10-24 | 1 | -0/+10 |
| * | | | target/arm: Reorg NEON VLD/VST all elements | Richard Henderson | 2018-10-24 | 1 | -96/+74 |
| * | | | target/arm: Use gvec for NEON VLD all lanes | Richard Henderson | 2018-10-24 | 1 | -55/+26 |
| * | | | target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE | Richard Henderson | 2018-10-24 | 3 | -61/+60 |
| * | | | target/arm: Use gvec for NEON_3R_VML | Richard Henderson | 2018-10-24 | 3 | -122/+120 |
| * | | | target/arm: Use gvec for VSRI, VSLI | Richard Henderson | 2018-10-24 | 3 | -219/+179 |
| * | | | target/arm: Use gvec for VSRA | Richard Henderson | 2018-10-24 | 3 | -117/+130 |
| * | | | target/arm: Use gvec for VSHR, VSHL | Richard Henderson | 2018-10-24 | 1 | -22/+48 |
| * | | | target/arm: Use gvec for NEON_3R_VMUL | Richard Henderson | 2018-10-24 | 1 | -16/+15 |
| * | | | target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG | Richard Henderson | 2018-10-24 | 1 | -8/+8 |
| * | | | target/arm: Use gvec for NEON_3R_VADD_VSUB insns | Richard Henderson | 2018-10-24 | 1 | -19/+10 |
| * | | | target/arm: Use gvec for NEON_3R_LOGIC insns | Richard Henderson | 2018-10-24 | 3 | -105/+124 |
| * | | | target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) | Richard Henderson | 2018-10-24 | 1 | -25/+36 |
| * | | | target/arm: Use gvec for NEON VDUP | Richard Henderson | 2018-10-24 | 1 | -27/+36 |
| * | | | target/arm: Mark some arrays const | Richard Henderson | 2018-10-24 | 1 | -2/+2 |
