summaryrefslogtreecommitdiffstats
path: root/target
Commit message (Expand)AuthorAgeFilesLines
* Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20181108' into...Peter Maydell2018-11-0811-384/+767
|\
| * ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HVSuraj Jitindar Singh2018-11-082-0/+24
| * target/ppc: Add one reg id for ptcrSuraj Jitindar Singh2018-11-081-5/+5
| * This patch fixes processing of rfi instructions in icount mode.Maria Klimushenkova2018-11-081-0/+12
| * target/ppc: fix mtmsr instruction for icountPavel Dovgalyuk2018-11-081-0/+12
| * target/ppc: Split out float_invalid_cvtRichard Henderson2018-11-081-39/+28Star
| * target/ppc: Split out float_invalid_op_divRichard Henderson2018-11-081-28/+24Star
| * target/ppc: Split out float_invalid_op_mulRichard Henderson2018-11-081-23/+20Star
| * target/ppc: Split out float_invalid_op_addsubRichard Henderson2018-11-081-34/+26Star
| * target/ppc: Introduce fp number classificationRichard Henderson2018-11-081-43/+51
| * target/ppc: Remove float_check_statusRichard Henderson2018-11-081-42/+35Star
| * target/ppc: Split up float_invalid_op_excpRichard Henderson2018-11-081-163/+181
| * target/ppc: add external PID supportRoman Kapl2018-11-088-45/+387
* | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2018-11-085-4/+34
|\ \ | |/ |/|
| * target/i386: Clear RF on SYSCALL instructionRudolf Marek2018-11-061-2/+2
| * x86: hv_evmcs CPU flag supportVitaly Kuznetsov2018-11-064-2/+32
* | target/arm: Fix ATS1Hx instructionsPeter Maydell2018-11-061-2/+2
* | target/arm: Set S and PTW in 64-bit PAR formatPeter Maydell2018-11-061-4/+6
* | target/arm: Remove can't-happen if() from handle_vec_simd_shli()Peter Maydell2018-11-061-5/+3Star
|/
* target/arm: Conditionalize some asserts on aarch32 supportRichard Henderson2018-11-022-2/+18
* Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' in...Peter Maydell2018-11-021-1/+1
|\
| * target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee2018-10-301-1/+1
* | Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-3.1-pull-request' ...Peter Maydell2018-11-022-4/+3Star
|\ \
| * | target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTEDLaurent Vivier2018-11-012-4/+3Star
| |/
* | Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20181031' into stagingPeter Maydell2018-11-013-375/+355Star
|\ \
| * | decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2018-10-313-375/+355Star
| |/
* | i386: Add PKU on Skylake-Server CPU modelTao Xu2018-10-311-0/+4
* | i386: Add new model of Cascadelake-ServerTao Xu2018-10-311-0/+54
* | x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIESRobert Hoo2018-10-313-1/+42
* | x86: Data structure changes to support MSR based featuresRobert Hoo2018-10-311-55/+142
* | kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctlRobert Hoo2018-10-311-0/+80
* | target/i386: Remove #ifdeffed-out icebp debugging hackPeter Maydell2018-10-311-6/+0Star
* | i386: correct cpu_x86_cpuid(0xd)Sebastian Andrzej Siewior2018-10-311-1/+1
|/
* target/mips: Amend MXU ASE overview noteAleksandar Markovic2018-10-291-10/+74
* target/mips: Move MXU_EN check one level higherAleksandar Markovic2018-10-291-271/+238Star
* target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek2018-10-291-7/+47
* target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek2018-10-291-7/+94
* target/mips: Add emulation of MXU instruction D16MACCraig Janeczek2018-10-291-3/+87
* target/mips: Add emulation of MXU instruction D16MULCraig Janeczek2018-10-291-3/+63
* target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek2018-10-291-3/+87
* target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic2018-10-291-18/+23
* target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek2018-10-291-6/+85
* target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek2018-10-291-1/+18
* target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek2018-10-291-0/+10
* target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek2018-10-291-0/+6
* target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic2018-10-291-0/+6
* target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek2018-10-291-0/+6
* target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic2018-10-291-0/+6
* target/mips: Add MXU decoding engineAleksandar Markovic2018-10-291-2/+1141
* target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic2018-10-291-0/+8
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-02-20 03:37:41 +0100