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* target/ppc: Fix vslv and vsrvAnton Blanchard2019-05-291-7/+7
* target/ppc: Fix xxbrq, xxbrwAnton Blanchard2019-05-291-2/+2
* target/ppc: Fix xvxsigdpAnton Blanchard2019-05-291-1/+1
* target/ppc/kvm: Fix trace typoBoxuan Li2019-05-292-2/+2
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2...Peter Maydell2019-05-2813-62/+79
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| * target/mips: convert UHI_plog to use common semihosting codeAlex Bennée2019-05-281-6/+6
| * target/mips: only build mips-semi for softmmuAlex Bennée2019-05-283-1/+12
| * target/arm: correct return values for WRITE/READ in arm-semiAlex Bennée2019-05-281-8/+12
| * target/arm: add LOG_UNIMP messages to arm-semiAlex Bennée2019-05-281-2/+3
| * target/arm: use the common interface for WRITE0/WRITEC in arm-semiAlex Bennée2019-05-281-25/+4Star
| * target/arm: fixup some of the commentary for arm-semiAlex Bennée2019-05-281-9/+31
| * semihosting: move semihosting configuration into its own directoryAlex Bennée2019-05-2811-11/+11
* | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v...Peter Maydell2019-05-286-202/+674
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| * | target/mips: realign comments to fix checkpatch warningsJules Irenge2019-05-261-12/+22
| * | target/mips: add or remove space to fix checkpatch errorsJules Irenge2019-05-261-81/+94
| * | mips: Decide to map PAGE_EXEC in map_addressJakub Jermář2019-05-261-5/+8
| * | target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic2019-05-263-18/+71
| * | target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic2019-05-263-21/+59
| * | target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic2019-05-263-21/+67
| * | target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic2019-05-261-20/+180
| * | target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic2019-05-261-20/+168
| * | target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic2019-05-261-2/+2
| * | target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic2019-05-261-2/+3
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* | target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens2019-05-241-1/+3
* | target/riscv: More accurate handling of `sip` CSRJonathan Behrens2019-05-241-2/+5
* | target/riscv: Add checks for several RVC reserved operandsRichard Henderson2019-05-242-3/+14
* | target/riscv: Add the HGATP register masksAlistair Francis2019-05-241-0/+11
* | target/riscv: Add the HSTATUS register masksAlistair Francis2019-05-241-0/+18
* | target/riscv: Add Hypervisor CSR macrosAlistair Francis2019-05-241-3/+6
* | target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis2019-05-241-9/+8Star
* | target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis2019-05-241-3/+2Star
* | target/riscv: Improve the scause logicAlistair Francis2019-05-241-1/+1
* | target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2019-05-242-8/+27
* | target/riscv: Mark privilege level 2 as reservedAlistair Francis2019-05-241-1/+1
* | target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-242-0/+16
* | target/riscv: Create settable CPU propertiesAlistair Francis2019-05-242-0/+57
* | target/riscv: Remove spaces from register namesRichard Henderson2019-05-241-8/+8
* | target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-242-9/+24
* | target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson2019-05-246-151/+67Star
* | target/riscv: Use pattern groups in insn16.decodeRichard Henderson2019-05-243-69/+29Star
* | target/riscv: Merge argument decode for RVC shiftiRichard Henderson2019-05-243-53/+12Star
* | target/riscv: Merge argument sets for insn32 and insn16Richard Henderson2019-05-242-170/+58Star
* | target/riscv: Use --static-decode for decodetreeRichard Henderson2019-05-242-7/+4Star
* | target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-242-3/+25
* | RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-243-12/+32
* | target/riscv: Do not allow sfence.vma from user modeJonathan Behrens2019-05-241-3/+4
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* arm: Remove unnecessary includes of hw/arm/arm.hPeter Maydell2019-05-236-6/+0Star
* target/arm: Fix vector operation segfaultAlistair Francis2019-05-231-2/+2
* target/arm: Simplify BFXIL expansionRichard Henderson2019-05-231-3/+3
* target/arm: Use extract2 for EXTRRichard Henderson2019-05-231-16/+18
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