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* Merge tag 'pull-request-2022-07-05' of https://gitlab.com/thuth/qemu into sta...Richard Henderson2022-07-051-7/+0Star
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| * disas: Remove libvixl disassemblerThomas Huth2022-07-051-7/+0Star
* | target/loongarch: Clean up tlb when cpu resetSong Gao2022-07-051-0/+1
* | target/loongarch: Add lock when writing timer clear regXiaojuan Yang2022-07-041-0/+2
* | target/loongarch: Fix the meaning of ECFG reg's VS fieldXiaojuan Yang2022-07-041-0/+4
* | target/loongarch: Update READMESong Gao2022-07-041-2/+37
* | target/loongarch: Adjust functions and structure to support user-modeSong Gao2022-07-046-1/+72
* | target/loongarch: remove unused include hw/loader.hSong Gao2022-07-041-1/+0Star
* | target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exceptionSong Gao2022-07-042-2/+4
* | target/loongarch: Fix missing update CSR_BADVSong Gao2022-07-041-4/+6
* | target/loongarch: remove badaddr from CPULoongArchSong Gao2022-07-042-3/+1Star
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* target/riscv: Update default priority table for local interruptsAnup Patel2022-07-032-70/+66Star
* target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel2022-07-032-168/+6Star
* target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel2022-07-031-1/+1
* target/riscv: Don't force update priv spec version to latestAnup Patel2022-07-031-4/+8
* target/riscv: Ibex: Support priv version 1.11Alistair Francis2022-07-031-1/+1
* target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis2022-07-031-1/+1
* target/riscv: Support mcycle/minstret write operationAtish Patra2022-07-036-53/+213
* target/riscv: Add support for hpmcounters/hpmeventsAtish Patra2022-07-033-152/+331
* target/riscv: Implement mcountinhibit CSRAtish Patra2022-07-034-0/+32
* target/riscv: pmu: Make number of counters configurableAtish Patra2022-07-033-36/+63
* target/riscv: pmu: Rename the counters extension to pmuAtish Patra2022-07-033-5/+5
* target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra2022-07-031-0/+51
* target/riscv: Fix PMU CSR predicate functionAtish Patra2022-07-031-4/+7
* target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre2022-07-031-0/+3
* target/riscv: Minimize the calls to decode_save_opcRichard Henderson2022-07-034-9/+17
* target/riscv: Remove generate_exception_mtvalRichard Henderson2022-07-031-9/+2Star
* target/riscv: Set env->bins in gen_exception_illegalRichard Henderson2022-07-031-0/+2
* target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo2022-07-031-6/+2Star
* target/nios2: Move nios2-semi.c to nios2_softmmu_ssRichard Henderson2022-06-282-7/+2Star
* target/nios2: Eliminate nios2_semi_is_lseekRichard Henderson2022-06-281-36/+23Star
* target/mips: Drop pread and pwrite syscalls from semihostingRichard Henderson2022-06-281-32/+7Star
* target/mips: Add UHI errno valuesRichard Henderson2022-06-281-0/+40
* target/mips: Use an exception for semihostingRichard Henderson2022-06-2810-21/+19Star
* target/m68k: Make semihosting system onlyRichard Henderson2022-06-282-38/+4Star
* target/m68k: Eliminate m68k_semi_is_fseekRichard Henderson2022-06-281-32/+23Star
* gdbstub: Adjust gdb_syscall_complete_cb declarationRichard Henderson2022-06-282-12/+6Star
* semihosting: Split out common-semi-target.hRichard Henderson2022-06-282-0/+112
* include/exec: Move gdb_stat and gdb_timeval to gdbstub.hRichard Henderson2022-06-282-54/+8Star
* include/exec: Move gdb open flags to gdbstub.hRichard Henderson2022-06-282-16/+0Star
* semihosting: Return void from do_common_semihostingRichard Henderson2022-06-283-4/+4
* semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.hRichard Henderson2022-06-283-3/+3
* target/arm: Check V7VE as well as LPAE in arm_pamaxRichard Henderson2022-06-271-1/+7
* target/arm: Extend arm_pamax to more than aarch64Richard Henderson2022-06-271-8/+16
* target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.hRichard Henderson2022-06-272-36/+38
* target/arm: Add SVL to TB flagsRichard Henderson2022-06-274-1/+21
* target/arm: Introduce sve_vqm1_for_el_smRichard Henderson2022-06-272-9/+32
* target/arm: Add cpu properties for SMERichard Henderson2022-06-274-7/+124
* target/arm: Unexport aarch64_add_*_propertiesRichard Henderson2022-06-272-5/+2Star
* target/arm: Move arm_cpu_*_finalize to internals.hRichard Henderson2022-06-273-6/+5Star
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