summaryrefslogtreecommitdiffstats
path: root/target
Commit message (Expand)AuthorAgeFilesLines
* i386: introduce hyperv_feature_supported()Vitaly Kuznetsov2021-05-311-19/+30
* i386: stop using env->features[] for filling Hyper-V CPUIDsVitaly Kuznetsov2021-05-312-38/+43
* i386: always fill Hyper-V CPUID feature leaves from X86CPU dataVitaly Kuznetsov2021-05-311-9/+0Star
* i386: invert hyperv_spinlock_attempts setting logic with hv_passthroughVitaly Kuznetsov2021-05-311-5/+1Star
* i386: keep hyperv_vendor string up-to-dateVitaly Kuznetsov2021-05-312-10/+14
* i386: use better matching family/model/stepping for 'max' CPUDaniel P. Berrangé2021-05-311-0/+6
* i386: use better matching family/model/stepping for 'qemu64' CPUDaniel P. Berrangé2021-05-311-3/+3
* i386/cpu_dump: support AVX512 ZMM regs dumpRobert Hoo2021-05-311-15/+48
* target/i386/cpu: Constify X86CPUDefinitionPhilippe Mathieu-Daudé2021-05-311-6/+7
* target/i386/cpu: Constify CPUCachesPhilippe Mathieu-Daudé2021-05-311-4/+4
* i386: Document when features can be added to kvm_default_propsEduardo Habkost2021-05-311-0/+5
* target/i386: Add CPU model versions supporting 'xsaves'Vitaly Kuznetsov2021-05-311-56/+94
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into...Peter Maydell2021-05-2825-79/+229
|\
| * hw/core: Constify TCGCPUOpsRichard Henderson2021-05-2721-22/+22
| * target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failedRichard Henderson2021-05-272-1/+5
| * cpu: Move CPUClass::get_paging_enabled to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+3
| * cpu: Move CPUClass::get_memory_mapping to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
| * cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-2719-19/+19
| * cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-272-2/+2
| * cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-275-13/+11Star
| * cpu: Move CPUClass::get_crash_info to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-272-2/+2
| * cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-272-4/+2Star
| * cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-277-7/+7
| * cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-2719-0/+146
| * cpu: Move AVR target vmsd field from CPUClass to DeviceClassPhilippe Mathieu-Daudé2021-05-272-3/+3
| * cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-278-9/+8Star
| * cpu: Assert DeviceClass::vmsd is NULL on user emulationPhilippe Mathieu-Daudé2021-05-272-3/+6
* | Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.1-pull-request' ...Peter Maydell2021-05-272-8/+51
|\ \
| * | target/m68k: implement m68k "any instruction" trace modeMark Cave-Ayland2021-05-262-7/+28
| * | target/m68k: introduce gen_singlestep_exception() functionMark Cave-Ayland2021-05-261-4/+13
| * | target/m68k: call gen_raise_exception() directly if single-stepping in gen_jm...Mark Cave-Ayland2021-05-261-1/+3
| * | target/m68k: introduce is_singlestepping() functionMark Cave-Ayland2021-05-261-4/+15
| |/
* / i386/cpu: Expose AVX_VNNI instruction to guestYang Zhong2021-05-262-2/+4
|/
* target/arm: Enable SVE2 and related extensionsRichard Henderson2021-05-253-0/+16
* target/arm: Implement integer matrix multiply accumulateRichard Henderson2021-05-257-0/+169
* target/arm: Implement aarch32 VSUDOT, VUSDOTRichard Henderson2021-05-253-0/+38
* target/arm: Split decode of VSDOT and VUDOTRichard Henderson2021-05-252-11/+28
* target/arm: Split out do_neon_dddaRichard Henderson2021-05-251-52/+38Star
* target/arm: Fix decode for VDOT (indexed)Richard Henderson2021-05-252-3/+3
* target/arm: Remove unused fpst from VDOT_scalarRichard Henderson2021-05-251-3/+0Star
* target/arm: Split out do_neon_ddda_fpstRichard Henderson2021-05-251-55/+43Star
* target/arm: Implement aarch64 SUDOT, USDOTRichard Henderson2021-05-252-0/+30
* target/arm: Implement SVE2 fp multiply-add longStephen Long2021-05-254-0/+141
* target/arm: Move endian adjustment macros to vec_internal.hRichard Henderson2021-05-253-28/+24Star
* target/arm: Implement SVE2 bitwise shift immediateStephen Long2021-05-254-0/+133
* target/arm: Implement 128-bit ZIP, UZP, TRNRichard Henderson2021-05-254-8/+90
* target/arm: Implement SVE2 LD1RORichard Henderson2021-05-252-0/+97
* target/arm: Tidy do_ldrqRichard Henderson2021-05-251-9/+4Star
* target/arm: Share table of sve load functionsRichard Henderson2021-05-251-128/+126Star
* target/arm: Implement SVE2 FLOGBStephen Long2021-05-254-0/+119
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-01 19:42:15 +0100