| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Implement fp16 for Neon float-integer VCVT | Peter Maydell | 2020-09-01 | 3 | -11/+42 |
| * | target/arm: Implement fp16 for Neon pairwise fp ops | Peter Maydell | 2020-09-01 | 3 | -26/+68 |
| * | target/arm: Implement fp16 for Neon VRSQRTS | Peter Maydell | 2020-09-01 | 4 | -36/+34 |
| * | target/arm: Implement fp16 for Neon VRECPS | Peter Maydell | 2020-09-01 | 4 | -34/+35 |
| * | target/arm: Implement fp16 for Neon fp compare-vs-0 | Peter Maydell | 2020-09-01 | 3 | -28/+45 |
| * | target/arm: Implement fp16 for Neon VFMA, VMFS | Peter Maydell | 2020-09-01 | 3 | -91/+40 |
| * | target/arm: Implement fp16 for Neon VMLA, VMLS operations | Peter Maydell | 2020-09-01 | 3 | -31/+50 |
| * | target/arm: Implement fp16 for Neon VMAXNM, VMINNM | Peter Maydell | 2020-09-01 | 3 | -8/+27 |
| * | target/arm: Implement fp16 for Neon VMAX, VMIN | Peter Maydell | 2020-09-01 | 3 | -3/+14 |
| * | target/arm: Implement fp16 for VACGE, VACGT | Peter Maydell | 2020-09-01 | 3 | -2/+34 |
| * | target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons | Peter Maydell | 2020-09-01 | 3 | -3/+56 |
| * | target/arm: Implement fp16 for Neon VABS, VNEG of floats | Peter Maydell | 2020-09-01 | 1 | -6/+28 |
| * | target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec | Peter Maydell | 2020-09-01 | 1 | -2/+29 |
| * | target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL | Peter Maydell | 2020-09-01 | 3 | -17/+26 |
| * | target/arm: Implement VFP fp16 VMOV between gp and halfprec registers | Peter Maydell | 2020-09-01 | 2 | -0/+35 |
| * | target/arm: Implement new VFP fp16 insn VMOVX | Peter Maydell | 2020-09-01 | 2 | -0/+28 |
| * | target/arm: Implement new VFP fp16 insn VINS | Peter Maydell | 2020-09-01 | 2 | -0/+31 |
| * | target/arm: Implement VFP fp16 VRINT* | Peter Maydell | 2020-09-01 | 5 | -8/+122 |
| * | target/arm: Implement VFP fp16 VSEL | Peter Maydell | 2020-09-01 | 2 | -6/+16 |
| * | target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode | Peter Maydell | 2020-09-01 | 2 | -10/+28 |
| * | target/arm: Implement VFP fp16 VCVT between float and fixed-point | Peter Maydell | 2020-09-01 | 2 | -0/+61 |
| * | target/arm: Use macros instead of open-coding fp16 conversion helpers | Peter Maydell | 2020-09-01 | 2 | -80/+12 |
| * | target/arm: Make VFP_CONV_FIX macros take separate float type and float size | Peter Maydell | 2020-09-01 | 1 | -23/+23 |
| * | target/arm: Implement VFP fp16 VCVT between float and integer | Peter Maydell | 2020-09-01 | 2 | -0/+69 |
| * | target/arm: Implement VFP fp16 VLDR and VSTR | Peter Maydell | 2020-09-01 | 2 | -2/+36 |
| * | target/arm: Implement VFP fp16 VCMP | Peter Maydell | 2020-09-01 | 4 | -7/+51 |
| * | target/arm: Implement VFP fp16 for VMOV immediate | Peter Maydell | 2020-09-01 | 2 | -0/+24 |
| * | target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT | Peter Maydell | 2020-09-01 | 4 | -0/+55 |
| * | target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp() | Peter Maydell | 2020-09-01 | 1 | -35/+14 |
| * | target/arm: Implement VFP fp16 for fused-multiply-add | Peter Maydell | 2020-09-01 | 4 | -0/+77 |
| * | target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS | Peter Maydell | 2020-09-01 | 1 | -37/+13 |
| * | target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL | Peter Maydell | 2020-09-01 | 4 | -0/+95 |
| * | target/arm: Implement VFP fp16 for VFP_BINOP operations | Peter Maydell | 2020-09-01 | 5 | -0/+106 |
| * | target/arm: Use correct ID register check for aa32_fp16_arith | Peter Maydell | 2020-09-01 | 1 | -6/+1 |
| * | target/arm: Remove local definitions of float constants | Peter Maydell | 2020-09-01 | 3 | -19/+0 |
| * | softfloat: Implement the full set of comparisons for float16 | Kito Cheng | 2020-08-28 | 1 | -25/+0 |
| * | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828'... | Peter Maydell | 2020-08-28 | 10 | -398/+446 |
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| | * | target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd | Richard Henderson | 2020-08-28 | 3 | -10/+81 |
| | * | target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd | Richard Henderson | 2020-08-28 | 3 | -0/+73 |
| | * | target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd | Richard Henderson | 2020-08-28 | 3 | -4/+45 |
| | * | target/arm: Generalize inl_qrdmlah_* helper functions | Richard Henderson | 2020-08-28 | 1 | -51/+29 |
| | * | target/arm: Tidy SVE tszimm shift formats | Richard Henderson | 2020-08-28 | 1 | -19/+16 |
| | * | target/arm: Split out gen_gvec_ool_zz | Richard Henderson | 2020-08-28 | 1 | -8/+12 |
| | * | target/arm: Split out gen_gvec_ool_zzz | Richard Henderson | 2020-08-28 | 1 | -35/+18 |
| | * | target/arm: Split out gen_gvec_ool_zzp | Richard Henderson | 2020-08-28 | 1 | -15/+14 |
| | * | target/arm: Merge helper_sve_clr_* and helper_sve_movz_* | Richard Henderson | 2020-08-28 | 3 | -92/+32 |
| | * | target/arm: Split out gen_gvec_ool_zzzp | Richard Henderson | 2020-08-28 | 1 | -19/+16 |
| | * | target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp | Richard Henderson | 2020-08-28 | 1 | -23/+8 |
| | * | target/arm: Clean up 4-operand predicate expansion | Richard Henderson | 2020-08-28 | 1 | -68/+43 |
| | * | target/arm: Merge do_vector2_p into do_mov_p | Richard Henderson | 2020-08-28 | 1 | -13/+6 |
