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* ppc/kvm: Handle the "family" CPU via alias instead of registering new typesThomas Huth2017-02-011-13/+23
* target/ppc/mmu_hash64: Fix incorrect shift value in amr calculationSuraj Jitindar Singh2017-02-011-1/+1
* target/ppc/mmu_hash64: Fix printing unsigned as signed intSuraj Jitindar Singh2017-02-011-2/+2
* tcg/POWER9: NOOP the cp_abort instructionSuraj Jitindar Singh2017-02-011-0/+5
* target/ppc/debug: Print LPCR register value if register existsSuraj Jitindar Singh2017-02-011-0/+3
* target-ppc: Add xststdc[sp, dp, qp] instructionsNikunj A Dadhania2017-02-015-8/+69
* target-ppc: Add xvtstdc[sp,dp] instructionsNikunj A Dadhania2017-02-015-2/+55
* target/ppc/cpu-models: Fix/remove bad CPU aliasesThomas Huth2017-01-311-20/+2Star
* target/ppc: Remove unused POWERPC_FAMILY(POWER)Thomas Huth2017-01-311-22/+0Star
* spapr: clock should count only if vm is runningLaurent Vivier2017-01-311-0/+3
* target/ppc: Add pcr_supported to POWER9 cpu class definitionSuraj Jitindar Singh2017-01-312-0/+3
* powerpc/cpu-models: rename ISAv3.00 logical PVR definitionSuraj Jitindar Singh2017-01-311-1/+1
* target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania2017-01-314-9/+24
* target-ppc: Add xsmulqp instructionBharata B Rao2017-01-314-0/+38
* target-ppc: Add xsdivqp instructionBharata B Rao2017-01-314-0/+39
* target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao2017-01-314-0/+31
* target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao2017-01-311-12/+8Star
* ppc: Implement bcdutrunc. instructionJose Ricardo Ziviani2017-01-314-1/+57
* ppc: Implement bcdtrunc. instructionJose Ricardo Ziviani2017-01-314-2/+45
* target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao2017-01-314-0/+46
* target-ppc: Add xvxsigdp instructionNikunj A Dadhania2017-01-312-0/+41
* target-ppc: Add xvxsigsp instructionNikunj A Dadhania2017-01-314-0/+24
* target-ppc: Add xvxexpdp instructionNikunj A Dadhania2017-01-312-0/+18
* target-ppc: Add xvxexpsp instructionNikunj A Dadhania2017-01-312-0/+18
* target-ppc: Add xviexpdp instructionNikunj A Dadhania2017-01-312-0/+27
* target-ppc: Add xviexpsp instructionNikunj A Dadhania2017-01-312-0/+28
* target-ppc: Add xsiexpqp instructionNikunj A Dadhania2017-01-312-0/+23
* target-ppc: Add xsiexpdp instructionNikunj A Dadhania2017-01-312-0/+21
* ppc: Implement bcdsr. instructionJose Ricardo Ziviani2017-01-314-0/+52
* ppc: Implement bcdus. instructionJose Ricardo Ziviani2017-01-314-1/+46
* ppc: Implement bcds. instructionJose Ricardo Ziviani2017-01-314-1/+46
* target-ppc: xscvqpdp zero VSRNikunj A Dadhania2017-01-311-1/+1
* ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macroJose Ricardo Ziviani2017-01-311-3/+3
* target-ppc: Add xscvqpdp instructionBharata B Rao2017-01-314-0/+31
* target-ppc: Add xscvdpqp instructionBharata B Rao2017-01-314-0/+48
* target-ppc: Add xsaddqp instructionsBharata B Rao2017-01-315-0/+41
* ppc: Add ppc_set_compat_all()David Gibson2017-01-312-0/+38
* target-ppc: Add xsxsigqp instructionsNikunj A Dadhania2017-01-312-0/+30
* target-ppc: Add xsxsigdp instructionNikunj A Dadhania2017-01-312-0/+30
* target-ppc: Add xsxexpqp instructionNikunj A Dadhania2017-01-312-0/+16
* target-ppc: Add xsxexpdp instructionNikunj A Dadhania2017-01-312-0/+17
* target-ppc: Use correct precision for FPRF settingBharata B Rao2017-01-312-2/+3
* target-ppc: Add xscvdphp, xscvhpdpBharata B Rao2017-01-315-0/+42
* target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64Bharata B Rao2017-01-313-70/+73
* target-ppc: Replace isden by float64_is_zero_or_denormalBharata B Rao2017-01-311-10/+1Star
* target-ppc: Use float64 arg in helper_compute_fprf()Bharata B Rao2017-01-311-9/+7Star
* target-ppc: Add xxinsertw instructionNikunj A Dadhania2017-01-314-2/+30
* target-ppc: Add xxextractuw instructionNikunj A Dadhania2017-01-314-0/+62
* ppc: Validate compatibility modes when settingDavid Gibson2017-01-312-0/+43
* ppc: Rewrite ppc_get_compat_smt_threads()David Gibson2017-01-313-21/+19Star
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