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* hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VMMarc Zyngier2021-09-131-1/+6
* target/sparc: Drop use of gen_io_end()Peter Maydell2021-09-081-15/+10Star
* s390x/cpumodel: Add more feature to gen16 default modelChristian Borntraeger2021-09-071-1/+7
* hw/s390x/s390-skeys: lazy storage key enablement under TCGDavid Hildenbrand2021-09-062-0/+17
* s390x/mmu_helper: avoid setting the storage key if nothing changedDavid Hildenbrand2021-09-061-4/+7
* s390x/mmu_helper: move address validation into mmu_translate*()David Hildenbrand2021-09-064-29/+24Star
* s390x/mmu_helper: fixup mmu_translate() documentationDavid Hildenbrand2021-09-061-1/+2
* s390x/mmu_helper: no need to pass access type to mmu_translate_asce()David Hildenbrand2021-09-061-2/+2
* s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKEDavid Hildenbrand2021-09-064-16/+35
* s390x/tcg: convert real to absolute address for RRBE, SSKE and ISKEDavid Hildenbrand2021-09-061-0/+3
* s390x/tcg: fix ignoring bit 63 when setting the storage key in SSKEDavid Hildenbrand2021-09-061-1/+1
* s390x/tcg: wrap address for RRBEDavid Hildenbrand2021-09-061-3/+4
* s390x/ioinst: Fix wrong MSCH alignment check on little endianDavid Hildenbrand2021-09-061-1/+1
* s390x/tcg: fix and optimize SPX (SET PREFIX)David Hildenbrand2021-09-061-1/+14
* target-arm: Add support for Fujitsu A64FXShuuichirou Ishii2021-09-011-0/+48
* target/arm: Enable MVE in Cortex-M55Peter Maydell2021-09-011-5/+2Star
* target/arm: Implement MVE VRINT insnsPeter Maydell2021-09-014-0/+93
* target/arm: Implement MVE VCVT between single and half precisionPeter Maydell2021-09-014-0/+108
* target/arm: Implement MVE VCVT with specified rounding modePeter Maydell2021-09-014-0/+105
* target/arm: Implement MVE VCVT between fp and integerPeter Maydell2021-09-012-0/+39
* target/arm: Implement MVE VCVT between floating and fixed pointPeter Maydell2021-09-014-0/+82
* target/arm: Implement MVE fp scalar comparisonsPeter Maydell2021-09-014-24/+131
* target/arm: Implement MVE fp vector comparisonsPeter Maydell2021-09-014-6/+137
* target/arm: Implement MVE FP max/min across vectorPeter Maydell2021-09-014-6/+102
* target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell2021-09-014-3/+56
* target/arm: Implement MVE scalar fp insnsPeter Maydell2021-09-014-6/+85
* target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell2021-09-014-0/+42
* target/arm: Implement MVE VCMUL and VCMLAPeter Maydell2021-09-014-8/+139
* target/arm: Implement MVE VFMA and VFMSPeter Maydell2021-09-014-0/+48
* target/arm: Implement MVE VCADDPeter Maydell2021-09-014-1/+57
* target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell2021-09-014-0/+42
* target/arm: Implement MVE VADD (floating-point)Peter Maydell2021-09-016-6/+76
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-012-61/+26Star
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-012-210/+57Star
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60Star
* target/riscv: Use {get,dest}_gpr for RVFRichard Henderson2021-09-011-76/+70Star
* target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6Star
* target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19Star
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-013-66/+132
* target/riscv: Fix hgeie, hgeipRichard Henderson2021-09-011-18/+8Star
* target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson2021-09-011-8/+15
* target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
* target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10Star
* target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-013-202/+125Star
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-012-23/+15Star
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-012-233/+234
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-012-127/+127
* target/riscv: Use gen_arith for mulh and mulhuRichard Henderson2021-09-011-22/+18Star
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-012-50/+8Star
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