summaryrefslogtreecommitdiffstats
path: root/target
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt2020-03-051-2/+2
* target/arm: Clean address for DC ZVARichard Henderson2020-03-051-1/+1
* target/arm: Use DEF_HELPER_FLAGS for helper_dc_zvaRichard Henderson2020-03-051-1/+1
* target/arm: Move helper_dc_zva to helper-a64.cRichard Henderson2020-03-054-94/+92Star
* target/arm: Apply TBI to ESR_ELx in helper_exception_returnRichard Henderson2020-03-051-1/+22
* target/arm: Introduce core_to_aa64_mmu_idxRichard Henderson2020-03-052-1/+7
* target/arm: Optimize cpu_mmu_indexRichard Henderson2020-03-052-15/+13Star
* target/arm: Replicate TBI/TBID bits for single range regimesRichard Henderson2020-03-051-2/+4
* target/arm: Honor the HCR_EL2.TTLB bitRichard Henderson2020-03-051-30/+55
* target/arm: Honor the HCR_EL2.TPU bitRichard Henderson2020-03-051-20/+31
* target/arm: Honor the HCR_EL2.TPCP bitRichard Henderson2020-03-051-8/+31
* target/arm: Honor the HCR_EL2.TACR bitRichard Henderson2020-03-051-4/+14
* target/arm: Honor the HCR_EL2.TSW bitRichard Henderson2020-03-051-6/+16
* target/arm: Honor the HCR_EL2.{TVM,TRVM} bitsRichard Henderson2020-03-051-27/+55
* target/arm: Improve masking in arm_hcr_el2_effRichard Henderson2020-03-051-4/+27
* target/arm: Remove EL2 and EL3 setup from user-onlyRichard Henderson2020-03-051-6/+0Star
* target/arm: Disable has_el2 and has_el3 for user-onlyRichard Henderson2020-03-051-2/+4
* target/arm: Add HCR_EL2 bit definitions from ARMv8.6Richard Henderson2020-03-051-0/+7
* target/arm: Improve masking of HCR/HCR2 RES0 bitsRichard Henderson2020-03-051-13/+25
* target/arm: Implement (trivially) ARMv8.2-TTCNPPeter Maydell2020-03-053-0/+7
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell2020-03-0310-133/+1223
|\
| * target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-273-4/+92
| * target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-272-0/+6
| * target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-274-4/+15
| * target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-276-0/+62
| * target/riscv: Set htval and mtval2 on execptionsAlistair Francis2020-02-271-0/+10
| * target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis2020-02-271-6/+18
| * target/riscv: Implement second stage MMUAlistair Francis2020-02-272-19/+175
| * target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
| * target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis2020-02-271-1/+15
| * target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis2020-02-271-0/+13
| * target/riscv: Disable guest FP support based on virtual statusAlistair Francis2020-02-271-0/+3
| * target/riscv: Only set TB flags with FP status if enabledAlistair Francis2020-02-271-1/+4
| * target/riscv: Remove the hret instructionAlistair Francis2020-02-272-6/+0Star
| * target/riscv: Add hfence instructionsAlistair Francis2020-02-272-9/+54
| * target/riscv: Add Hypervisor trap return supportAlistair Francis2020-02-271-10/+52
| * target/riscv: Add hypvervisor trap supportAlistair Francis2020-02-271-10/+59
| * target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis2020-02-271-2/+3
| * target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis2020-02-271-0/+5
| * target/riscv: Add support for virtual interrupt settingAlistair Francis2020-02-271-5/+28
| * target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis2020-02-271-1/+12
| * target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis2020-02-271-4/+20
| * target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis2020-02-271-0/+3
| * target/riscv: Add virtual register swapping functionAlistair Francis2020-02-273-0/+79
| * target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis2020-02-271-0/+27
| * target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis2020-02-271-0/+116
| * target/riscv: Add Hypervisor CSR access functionsAlistair Francis2020-02-271-2/+134
| * target/riscv: Dump Hypervisor registers if enabledAlistair Francis2020-02-271-0/+33
| * target/riscv: Print priv and virt in disas logAlistair Francis2020-02-271-0/+8
| * target/riscv: Fix CSR perm checking for HS modeAlistair Francis2020-02-271-4/+14
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-12 11:53:41 +0200