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* Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210316' ↵Peter Maydell2021-03-178-73/+153
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging s390x updates: - get rid of legacy_s390_alloc() and phys_mem_set_alloc() - tcg: implement the MVPG condition-code-option bit - fix g_autofree variable handing in the pci vfio code - use official z15 names in the cpu model definitions # gpg: Signature made Tue 16 Mar 2021 10:04:21 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck-gitlab/tags/s390x-20210316: s390x/pci: Add missing initialization for g_autofree variables target/s390x: Store r1/r2 for page-translation exceptions during MVPG target/s390x: Implement the MVPG condition-code-option bit s390x/cpu_model: use official name for 8562 exec: Get rid of phys_mem_set_alloc() s390x/kvm: Get rid of legacy_s390_alloc() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/s390x: Store r1/r2 for page-translation exceptions during MVPGDavid Hildenbrand2021-03-154-21/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PoP states: When EDAT-1 does not apply, and a program interruption due to a page-translation exception is recognized by the MOVE PAGE instruction, the contents of the R1 field of the instruction are stored in bit positions 0-3 of location 162, and the contents of the R2 field are stored in bit positions 4-7. If [...] an ASCE-type, region-first-translation, region-second-translation, region-third-translation, or segment-translation exception was recognized, the contents of location 162 are unpredictable. So we have to write r1/r2 into the lowcore on page-translation exceptions. Simply handle all exceptions inside our mvpg helper now. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210315085449.34676-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * target/s390x: Implement the MVPG condition-code-option bitRichard Henderson2021-03-153-23/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the CCO bit is set, MVPG should not generate an exception but report page translation faults via a CC code. Create a new helper, access_prepare_nf, which can use probe_access_flags in non-faulting mode, and then handle watchpoints. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [thuth: Added logic to still inject protection exceptions] Signed-off-by: Thomas Huth <thuth@redhat.com> [david: Look at env->tlb_fill_exc to determine if there was an exception] Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210315085449.34676-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/cpu_model: use official name for 8562Cornelia Huck2021-03-151-2/+2
| | | | | | | | | | | | | | | | | | | | The single-frame z15 is called "z15 T02" (and the multi-frame z15 "z15 T01"). Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20210311132746.1777754-1-cohuck@redhat.com>
| * s390x/kvm: Get rid of legacy_s390_alloc()David Hildenbrand2021-03-151-38/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | legacy_s390_alloc() was required for dealing with the absence of the ESOP feature -- on old HW (< gen 10) and old z/VM versions (< 6.3). As z/VM v6.2 (and even v6.3) is no longer supported since 2017 [1] and we don't expect to have real users on such old hardware, let's drop legacy_s390_alloc(). Still check+report an error just in case someone still runs on such old z/VM environments, or someone runs under weird nested KVM setups (where we can manually disable ESOP via the CPU model). No need to check for KVM_CAP_GMAP - that should always be around on kernels that also have KVM_CAP_DEVICE_CTRL (>= v3.15). [1] https://www.ibm.com/support/lifecycle/search?q=z%2FVM Suggested-by: Cornelia Huck <cohuck@redhat.com> Suggested-by: Thomas Huth <thuth@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Halil Pasic <pasic@linux.ibm.com> Cc: Cornelia Huck <cohuck@redhat.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210303130916.22553-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | Merge remote-tracking branch 'remotes/philmd/tags/avr-20210315' into stagingPeter Maydell2021-03-151-4/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AVR patches queue - Only reset 'interrupt_request' mask once all interrupts executed - Documentation and typo fixes # gpg: Signature made Sun 14 Mar 2021 23:45:34 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/avr-20210315: target/avr: Fix interrupt execution target/avr: Fix some comment spelling errors hw/avr/arduino: List board schematic links hw/misc/led: Add yellow LED Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/avr: Fix interrupt executionIvanov Arkasha2021-03-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only one interrupt is in progress at the moment. It is only necessary to set to reset interrupt_request after all interrupts have been executed. Signed-off-by: Ivanov Arkasha <ivanovrkasha@gmail.com> Message-Id: <20210312164754.18437-1-arkaisp2021@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
| * | target/avr: Fix some comment spelling errorsLichang Zhao2021-03-151-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | I found that there are many spelling errors in the comments of qemu/target/avr. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: Lichang Zhao <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org> Message-Id: <20201009064449.2336-12-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
* | Merge remote-tracking branch ↵Peter Maydell2021-03-153-22/+20Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/bkoppelmann2/tags/pull-tricore-20210314' into staging - Added triboard with tc27x_soc - Cleaned up get_physical_address() - Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK insns # gpg: Signature made Sun 14 Mar 2021 13:53:11 GMT # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full] # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann2/tags/pull-tricore-20210314: target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 tricore: fixed faulty conditions for extr and imask target/tricore: Remove unused definitions target/tricore: Pass MMUAccessType to get_physical_address() target/tricore: Replace magic value by MMU_DATA_LOAD definition tricore: added triboard with tc27x_soc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/tricore: Fix OPC2_32_RRPW_EXTR for width=0Bastian Koppelmann2021-03-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if width was 0 we would run into the assertion: qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o The instruction manual specifies undefined behaviour for this case. So we bring this in line with the golden Infineon simlator 'tsim', which simply writes 0 to the result in case of width=0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| * | target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2Bastian Koppelmann2021-03-141-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | if r3+1 and r2 are the same then we would overwrite r2 with our first move and use the wrong result for the shift. Thus we store the result from the mov in a temp. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| * | tricore: fixed faulty conditions for extr and imaskAndreas Konopik2021-03-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the TC 1.3.1. Architecture Manual [1; page 174], results are undefined, if pos + width > 32 and not 31 or if width = 0. We found this error because of a different behavior between qemu-tricore and the real tricore processor. For pos + width = 32, qemu-tricore did not generate any intermediate code and ran into a different state compared to the real hardware. [1] https://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352 [BK: Add the why to the commit message] Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Message-Id: <20210211115329.8984-2-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| * | target/tricore: Remove unused definitionsPhilippe Mathieu-Daudé2021-03-141-12/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove these confusing and unused definitions. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127224255.3505711-4-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| * | target/tricore: Pass MMUAccessType to get_physical_address()Philippe Mathieu-Daudé2021-03-141-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'int access_type' and ACCESS_INT are unused, drop them. Provide the mmu_idx argument to match other targets. 'int rw' is actually the MMUAccessType, rename it. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127224255.3505711-3-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| * | target/tricore: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2021-03-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210127224255.3505711-2-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* | | Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into stagingPeter Maydell2021-03-147-3645/+2017Star
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS patches queue - Tidy up the GT64120 north bridge - Move XBurst Media eXtension Unit code to mxu_translate.c - Convert TX79 to decodetree # gpg: Signature made Sat 13 Mar 2021 22:44:44 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210313: (27 commits) target/mips/tx79: Salvage instructions description comment target/mips: Remove 'C790 Multimedia Instructions' dead code target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree target/mips/tx79: Move PCPYH opcode to decodetree target/mips/translate: Simplify PCPYH using deposit_i64() target/mips/translate: Make gen_rdhwr() public target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree target/mips: Use gen_load_gpr[_hi]() when possible target/mips: Extract MXU code to new mxu_translate.c file target/mips: Introduce mxu_translate_init() helper target/mips: Simplify decode_opc_mxu() ifdef'ry target/mips: Convert decode_ase_mxu() to decodetree prototype target/mips: Rename decode_opc_mxu() as decode_ase_mxu() target/mips: Move MUL opcode check from decode_mxu() to decode_legacy() target/mips: Use OPC_MUL instead of OPC__MXU_MUL target/mips: Pass instruction opcode to decode_opc_mxu() target/mips: Remove unused CPUMIPSState* from MXU functions target/mips: Remove XBurst Media eXtension Unit dead code target/mips: Rewrite complex ifdef'ry ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/mips/tx79: Salvage instructions description commentPhilippe Mathieu-Daudé2021-03-132-160/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This comment describing the tx79 opcodes is helpful. As we will implement these instructions in tx79_translate.c, move the comment there. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-15-f4bug@amsat.org>
| * | target/mips: Remove 'C790 Multimedia Instructions' dead codePhilippe Mathieu-Daudé2021-03-131-371/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have almost 400 lines of code full of /* TODO */ comments which end calling gen_reserved_instruction(). As we are not going to implement them, and all the caller's switch() default cases already call gen_reserved_instruction(), we can remove this altogether. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-14-f4bug@amsat.org>
| * | target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetreePhilippe Mathieu-Daudé2021-03-133-80/+48Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
| * | target/mips/tx79: Move PCPYH opcode to decodetreePhilippe Mathieu-Daudé2021-03-133-39/+27Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
| * | target/mips/translate: Simplify PCPYH using deposit_i64()Philippe Mathieu-Daudé2021-03-131-30/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the PCPYH (Parallel Copy Halfword) instruction by using multiple calls to deposit_i64() which can be optimized by some TCG backends. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
| * | target/mips/translate: Make gen_rdhwr() publicPhilippe Mathieu-Daudé2021-03-132-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | We will use gen_rdhwr() outside of translate.c, make it public. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
| * | target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetreePhilippe Mathieu-Daudé2021-03-133-25/+17Star
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
| * | target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetreePhilippe Mathieu-Daudé2021-03-136-12/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
| * | target/mips: Use gen_load_gpr[_hi]() when possiblePhilippe Mathieu-Daudé2021-03-131-23/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use gen_load_gpr[_hi]() instead of open coding it. Patch generated using the following spatch script: @gen_load_gpr@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx == 0) { - tcg_gen_movi_tl(tcg_reg, 0); -} else { - tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]); -} +gen_load_gpr(tcg_reg, reg_idx); @gen_load_gpr_hi@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx == 0) { - tcg_gen_movi_i64(tcg_reg, 0); -} else { - tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]); -} +gen_load_gpr_hi(tcg_reg, reg_idx); Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308131604.460693-1-f4bug@amsat.org>
| * | target/mips: Extract MXU code to new mxu_translate.c filePhilippe Mathieu-Daudé2021-03-133-1605/+1613
| | | | | | | | | | | | | | | | | | | | | | | | Extract 1600+ lines from the big translate.c into a new file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-14-f4bug@amsat.org>
| * | target/mips: Introduce mxu_translate_init() helperPhilippe Mathieu-Daudé2021-03-132-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper. Make it public and replace !TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to elide this code at preprocessing time. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
| * | target/mips: Simplify decode_opc_mxu() ifdef'ryPhilippe Mathieu-Daudé2021-03-132-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By making the prototype public and checking 'TARGET_LONG_BITS == 32' we let the compiler elide the decode_opc_mxu() call. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-12-f4bug@amsat.org>
| * | target/mips: Convert decode_ase_mxu() to decodetree prototypePhilippe Mathieu-Daudé2021-03-131-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | To easily convert MXU code to decodetree, making it return a boolean. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-11-f4bug@amsat.org>
| * | target/mips: Rename decode_opc_mxu() as decode_ase_mxu()Philippe Mathieu-Daudé2021-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use "decode_{isa,ase,ext}_$name()" function name pattern for public decodetree entrypoints. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-10-f4bug@amsat.org>
| * | target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()Philippe Mathieu-Daudé2021-03-131-14/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the check for MUL opcode from decode_opc_mxu() callee to decode_opc_legacy() caller, so we can simplify the ifdef'ry and elide the call in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-9-f4bug@amsat.org>
| * | target/mips: Use OPC_MUL instead of OPC__MXU_MULPhilippe Mathieu-Daudé2021-03-131-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already have a macro and definition to extract / check the Special2 MUL opcode. Use it instead of the unnecessary OPC__MXU_MUL macro. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-8-f4bug@amsat.org>
| * | target/mips: Pass instruction opcode to decode_opc_mxu()Philippe Mathieu-Daudé2021-03-131-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the next commit we'll make decode_opc_mxu() match decodetree prototype by returning a boolean. First pass ctx->opcode as an argument. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-7-f4bug@amsat.org>
| * | target/mips: Remove unused CPUMIPSState* from MXU functionsPhilippe Mathieu-Daudé2021-03-131-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | None of these MXU functions use their CPUMIPSState* env argument, remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-6-f4bug@amsat.org>
| * | target/mips: Remove XBurst Media eXtension Unit dead codePhilippe Mathieu-Daudé2021-03-131-1286/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All these unimplemented MXU opcodes end up calling gen_reserved_instruction() which is the default switch case in decode_opc_mxu(). The translate.c file is already big enough and hard to maintain, remove 1300 lines of unnecessary code and /* TODO */ comments. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-5-f4bug@amsat.org>
| * | target/mips: Rewrite complex ifdef'ryPhilippe Mathieu-Daudé2021-03-131-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | No need for this obfuscated ifdef'ry, KISS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-4-f4bug@amsat.org>
| * | target/mips/meson: Restrict mips-semi.c to TCGPhilippe Mathieu-Daudé2021-03-131-1/+1
| | | | | | | | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-3-f4bug@amsat.org>
| * | target/mips/meson: Introduce mips_tcg source setPhilippe Mathieu-Daudé2021-03-131-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Introduce the 'mips_tcg' source set to collect TCG specific files. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-2-f4bug@amsat.org>
* | | Merge remote-tracking branch ↵Peter Maydell2021-03-144-63/+80
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210314' into staging target-arm queue: * versal: Support XRAMs and XRAM controller * smmu: Various minor bug fixes * SVE emulation: fix bugs handling odd vector lengths * allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register value * tests/acceptance: fix orangepi-pc acceptance tests * hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() * hw/arm/virt: KVM: The IPA lower bound is 32 * npcm7xx: support MFT module * pl110, pxa2xx_lcd: tidy up template headers # gpg: Signature made Sun 14 Mar 2021 13:17:43 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210314: (39 commits) hw/display/pxa2xx: Inline template header hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header hw/display/pxa2xx: Apply brace-related coding style fixes to template header hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h hw/display/pxa2xx_lcd: Remove dest_width state field hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces hw/display/pl110: Remove use of BITS from pl110_template.h hw/display/pl110: Pull included-once parts of template header into pl110.c hw/display/pl110: Remove dead code for non-32-bpp surfaces tests/qtest: Test PWM fan RPM using MFT in PWM test hw/arm: Connect PWM fans in NPCM7XX boards hw/arm: Add MFT device to NPCM7xx Soc hw/misc: Add NPCM7XX MFT Module hw/misc: Add GPIOs for duty in NPCM7xx PWM hw/arm/virt: KVM: The IPA lower bound is 32 accel: kvm: Fix kvm_type invocation hw/timer/sse-timer: Propagate eventual error in sse_timer_realize() tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests tests/acceptance: update sunxi kernel from armbian to 5.10.16 tests/acceptance/boot_linux_console: change URL for test_arm_orangepi_bionic_20_08 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/virt: KVM: The IPA lower bound is 32Andrew Jones2021-03-122-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The virt machine already checks KVM_CAP_ARM_VM_IPA_SIZE to get the upper bound of the IPA size. If that bound is lower than the highest possible GPA for the machine, then QEMU will error out. However, the IPA is set to 40 when the highest GPA is less than or equal to 40, even when KVM may support an IPA limit as low as 32. This means KVM may fail the VM creation unnecessarily. Additionally, 40 is selected with the value 0, which means use the default, and that gets around a check in some versions of KVM, causing a difficult to debug fail. Always use the IPA size that corresponds to the highest possible GPA, unless it's lower than 32, in which case use 32. Also, we must still use 0 when KVM only supports the legacy fixed 40 bit IPA. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Message-id: 20210310135218.255205-3-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Update sve reduction vs simd_descRichard Henderson2021-03-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the reduction operations, we intentionally increase maxsz to the next power of 2, so as to fill out the reduction tree correctly. Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small vectors, so this triggers an assertion for vector sizes > 32 that are not themselves a power of 2. Pass the power-of-two value in the simd_data field instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Update WHILE for PREDDESCRichard Henderson2021-03-122-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since b64ee454a4a0, all predicate operations should be using these field macros for predicates. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Update CNTP for PREDDESCRichard Henderson2021-03-122-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since b64ee454a4a0, all predicate operations should be using these field macros for predicates. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Update BRKA, BRKB, BRKN for PREDDESCRichard Henderson2021-03-122-18/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since b64ee454a4a0, all predicate operations should be using these field macros for predicates. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Update find_last_active for PREDDESCRichard Henderson2021-03-122-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since b64ee454a4a0, all predicate operations should be using these field macros for predicates. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Fix sve_punpk_p vs odd vector lengthsRichard Henderson2021-03-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wrote too much with punpk1 with vl % 512 != 0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Fix sve_zip_p vs odd vector lengthsRichard Henderson2021-03-121-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wrote too much with low-half zip (zip1) with vl % 512 != 0. Adjust all of the x + (y << s) to x | (y << s) as a style fix. We only ever have exact overlap between D, M, and N. Therefore we only need a single temporary, and we do not need to check for partial overlap. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Fix sve_uzp_p vs odd vector lengthsRichard Henderson2021-03-121-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Missed out on compressing the second half of a predicate with length vl % 512 > 256. Adjust all of the x + (y << s) to x | (y << s) as a general style fix. Drop the extract64 because the input uint64_t are known to be already zero-extended from the current size of the predicate. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210309155305.11301-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' ↵Peter Maydell2021-03-124-24/+82
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Prepare MacOS ROM support: - add RTR instruction - fix unaligned access requirement - fix ATC bit (68040 MMU) # gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-6.0-pull-request: target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature target/m68k: reformat m68k_features enum target/m68k: don't set SSW ATC bit for physical bus errors target/m68k: implement rtr instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/m68k: add M68K_FEATURE_UNALIGNED_DATA featureMark Cave-Ayland2021-03-113-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the M68040UM Appendix D the requirement for data accesses to be word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the 68020 onwards will allow unaligned data accesses but at the cost of being less efficient. Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are not required to be word aligned, and don't perform the alignment on the stack pointer when taking an exception if this feature is not selected. This is required because the MacOS DAFB driver attempts to call an A-trap with a byte-aligned stack pointer during initialisation and without this the stack pointer is off by one when the A-trap returns. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308121155.2476-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 07:11:59 +0100