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* monitor: expose monitor_puts to rest of codeAlex Bennée2022-10-061-1/+1
* Merge tag 'pull-hex-20221003' of https://github.com/quic/qemu into stagingStefan Hajnoczi2022-10-059-137/+192
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| * Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEWMatheus Tavares Bernardino2022-10-031-1/+1
| * Hexagon (target/hexagon) move store size tracking to translationTaylor Simpson2022-09-303-28/+41
| * Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]Taylor Simpson2022-09-304-10/+17
| * Hexagon (target/hexagon) add instruction attributes from archlibTaylor Simpson2022-09-303-98/+133
* | Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2022-10-0531-107/+298
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| * | target/sh4: Fix TB_FLAG_UNALIGNRichard Henderson2022-10-044-74/+86
| * | accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-0415-19/+19
| * | hw/core: Add CPUClass.get_pcRichard Henderson2022-10-0421-0/+183
| * | accel/tcg: Suppress auto-invalidate in probe_access_internalRichard Henderson2022-10-041-4/+0Star
| * | accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFullRichard Henderson2022-10-043-10/+10
* | | Merge tag 'trivial-branch-for-7.2-pull-request' of https://gitlab.com/laurent...Stefan Hajnoczi2022-10-042-16/+10Star
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| * | | Drop superfluous conditionals around g_free()Markus Armbruster2022-10-042-16/+10Star
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* | | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2022-10-041-1/+1
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| * | target/i386/kvm: fix kvmclock_current_nsec: Assertion `time.tsc_timestamp <= ...Ray Zhang2022-10-011-1/+1
* | | target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEPJerome Forissier2022-09-291-1/+1
* | | target/arm: Rearrange cpu64.c so all the CPU initfns are togetherPeter Maydell2022-09-291-356/+356
* | | target/arm: Update SDCR_VALID_MASK to include SCCDPeter Maydell2022-09-291-1/+7
* | | target/arm: Make writes to MDCR_EL3 use PMU start/finish callsPeter Maydell2022-09-291-4/+14
* | | target/arm: Mark registers which call pmu_op_start() as ARM_CP_IOPeter Maydell2022-09-291-6/+6
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* | Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_viv...Stefan Hajnoczi2022-09-281-2/+4
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| * | linux-user/hppa: Dump IIR on register dumpHelge Deller2022-09-271-2/+4
* | | Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k ...Stefan Hajnoczi2022-09-273-6/+13
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| * | | target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privil...Mark Cave-Ayland2022-09-263-1/+8
| * | | target/m68k: increase size of m68k CPU features from uint32_t to uint64_tMark Cave-Ayland2022-09-262-5/+5
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* | | Merge tag 'pull-request-2022-09-26' of https://gitlab.com/thuth/qemu into sta...Stefan Hajnoczi2022-09-275-2/+277
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| * | | s390x/pci: enable for load/store interpretationMatthew Rosato2022-09-262-0/+8
| * | | target/s390x: support PRNO_TRNG instructionJason A. Donenfeld2022-09-262-0/+31
| * | | target/s390x: support SHA-512 extensionsJason A. Donenfeld2022-09-232-1/+237
| * | | s390x/tcg: Fix opcode for lzrfChristian Borntraeger2022-09-231-1/+1
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* | | target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu2022-09-274-15/+31
* | | target/riscv: rvv-1.0: Simplify vfwredsum codeYang Liu2022-09-271-46/+10Star
* | | target/riscv: debug: Add initial support of type 6 triggerFrank Chang2022-09-272-4/+188
* | | target/riscv: debug: Check VU/VS modes for type 2 triggerFrank Chang2022-09-271-0/+10
* | | target/riscv: debug: Create common trigger actions functionFrank Chang2022-09-272-2/+70
* | | target/riscv: debug: Introduce tinfo CSRFrank Chang2022-09-274-3/+18
* | | target/riscv: debug: Restrict the range of tselect value can be writtenFrank Chang2022-09-271-6/+3Star
* | | target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang2022-09-274-88/+48Star
* | | target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang2022-09-272-5/+12
* | | target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang2022-09-275-67/+140
* | | target/riscv: Check the correct exception cause in vector GDB stubFrank Chang2022-09-261-2/+2
* | | target/riscv: Set the CPU resetvec directlyAlistair Francis2022-09-263-15/+7Star
* | | target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xmlAndrew Burgess2022-09-261-30/+2Star
* | | target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li2022-09-261-4/+9
* | | target/riscv: Remove sideleg and sedelegRahul Pathak2022-09-261-2/+0Star
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* | Merge tag 'pull-target-arm-20220922' of https://git.linaro.org/people/pmaydel...Stefan Hajnoczi2022-09-266-282/+241Star
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| * target/arm: Add is_secure parameter to get_phys_addr_pmsav5Richard Henderson2022-09-221-2/+2
| * target/arm: Add secure parameter to get_phys_addr_pmsav7Richard Henderson2022-09-221-3/+2Star
| * target/arm: Add is_secure parameter to pmsav7_use_background_regionRichard Henderson2022-09-221-5/+5
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