bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/cris: Remove superfluous breaks	Liao Pingfang	2020-09-01	2	-6/+3
*	target/sh4: Remove superfluous breaks	Liao Pingfang	2020-09-01	1	-3/+0
*	target/ppc: Remove superfluous breaks	Liao Pingfang	2020-09-01	1	-5/+0
*	target/arm/kvm: Remove superfluous break	Liao Pingfang	2020-09-01	1	-1/+0
*	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828'...	Peter Maydell	2020-08-28	10	-398/+446
\|\
\| *	target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd	Richard Henderson	2020-08-28	3	-10/+81
\| *	target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd	Richard Henderson	2020-08-28	3	-0/+73
\| *	target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd	Richard Henderson	2020-08-28	3	-4/+45
\| *	target/arm: Generalize inl_qrdmlah_* helper functions	Richard Henderson	2020-08-28	1	-51/+29
\| *	target/arm: Tidy SVE tszimm shift formats	Richard Henderson	2020-08-28	1	-19/+16
\| *	target/arm: Split out gen_gvec_ool_zz	Richard Henderson	2020-08-28	1	-8/+12
\| *	target/arm: Split out gen_gvec_ool_zzz	Richard Henderson	2020-08-28	1	-35/+18
\| *	target/arm: Split out gen_gvec_ool_zzp	Richard Henderson	2020-08-28	1	-15/+14
\| *	target/arm: Merge helper_sve_clr_* and helper_sve_movz_*	Richard Henderson	2020-08-28	3	-92/+32
\| *	target/arm: Split out gen_gvec_ool_zzzp	Richard Henderson	2020-08-28	1	-19/+16
\| *	target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp	Richard Henderson	2020-08-28	1	-23/+8
\| *	target/arm: Clean up 4-operand predicate expansion	Richard Henderson	2020-08-28	1	-68/+43
\| *	target/arm: Merge do_vector2_p into do_mov_p	Richard Henderson	2020-08-28	1	-13/+6
\| *	target/arm: Rearrange {sve,fp}_check_access assert	Richard Henderson	2020-08-28	2	-11/+17
\| *	target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn	Richard Henderson	2020-08-28	1	-19/+24
\| *	target/arm: Split out gen_gvec_fn_zz	Richard Henderson	2020-08-28	1	-9/+10
\| *	target/arm: Fill in the WnR syndrome bit in mte_check_fail	Richard Henderson	2020-08-28	1	-4/+5
\| *	target/arm: Pass the entire mte descriptor to mte_check_fail	Richard Henderson	2020-08-28	1	-5/+5
\| *	target/arm: Clarify HCR_EL2 ARMCPRegInfo type	Philippe Mathieu-Daudé	2020-08-28	1	-1/+0
* \|	hvf: Move HVFState typedef to hvf.h	Eduardo Habkost	2020-08-27	1	-2/+2
\|/
*	target/riscv: Support the Virtual Instruction fault	Alistair Francis	2020-08-25	5	-6/+109
*	target/riscv: Return the exception from invalid CSR accesses	Alistair Francis	2020-08-25	2	-29/+35
*	target/riscv: Support the v0.6 Hypervisor extension CRSs	Alistair Francis	2020-08-25	2	-0/+43
*	target/riscv: Only support little endian guests	Alistair Francis	2020-08-25	1	-0/+5
*	target/riscv: Only support a single VSXL length	Alistair Francis	2020-08-25	1	-0/+9
*	target/riscv: Update the CSRs to the v0.6 Hyp extension	Alistair Francis	2020-08-25	1	-6/+8
*	target/riscv: Update the Hypervisor trap return/entry	Alistair Francis	2020-08-25	4	-26/+9
*	target/riscv: Fix the interrupt cause code	Alistair Francis	2020-08-25	1	-2/+3
*	target/riscv: Convert MSTATUS MTL to GVA	Alistair Francis	2020-08-25	3	-9/+26
*	target/riscv: Don't allow guest to write to htinst	Alistair Francis	2020-08-25	1	-1/+0
*	target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions	Alistair Francis	2020-08-25	1	-35/+25
*	target/riscv: Allow generating hlv/hlvx/hsv instructions	Alistair Francis	2020-08-25	6	-0/+474
*	target/riscv: Allow setting a two-stage lookup in the virt status	Alistair Francis	2020-08-25	3	-0/+21
*	Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging	Peter Maydell	2020-08-24	19	-415/+197691
\|\
\| *	target/xtensa: import DSP3400 core	Max Filippov	2020-08-21	6	-0/+173129
\| *	target/xtensa: import de233_fpu core	Max Filippov	2020-08-21	6	-0/+22538
\| *	target/xtensa: implement FPU division and square root	Max Filippov	2020-08-21	3	-0/+132
\| *	target/xtensa: add DFPU registers and opcodes	Max Filippov	2020-08-21	6	-34/+1413
\| *	target/xtensa: add DFPU option	Max Filippov	2020-08-21	2	-0/+25
\| *	target/xtensa: don't access BR regfile directly	Max Filippov	2020-08-21	3	-34/+42
\| *	target/xtensa: move FSR/FCR register accessors	Max Filippov	2020-08-21	1	-32/+32
\| *	target/xtensa: rename FPU2000 translators and helpers	Max Filippov	2020-08-21	3	-55/+57
\| *	target/xtensa: support copying registers up to 64 bits wide	Max Filippov	2020-08-21	2	-5/+22
\| *	target/xtensa: add geometry to xtensa_get_regfile_by_name	Max Filippov	2020-08-21	3	-10/+31
\| *	target/xtensa: implement NMI support	Max Filippov	2020-08-21	3	-9/+21