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* target/ppc: Fix QEMU crash with stxsdxGreg Kurz2019-03-291-1/+1
* target/ppc: Improve comment of bcctr used for spectre v2 mitigationGreg Kurz2019-03-291-1/+9
* target/ppc: Consolidate 64-bit server processor detection in a helperGreg Kurz2019-03-293-7/+11
* target/ppc: Enable "decrement and test CTR" version of bcctrGreg Kurz2019-03-291-15/+37
* target/ppc: Fix TCG temporary leaks in gen_bcond()Greg Kurz2019-03-291-0/+2
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2019-03-281-0/+11
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| * target/i386: sev: Do not pin the ram device memory regionSingh, Brijesh2019-03-181-0/+11
* | Merge remote-tracking branch 'remotes/xtensa/tags/20190326-xtensa' into stagingPeter Maydell2019-03-282-2/+0Star
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| * | target/xtensa: don't announce exit simcallMax Filippov2019-03-231-1/+0Star
| * | target/xtensa: fix break_dependency for repeated resourcesMax Filippov2019-03-221-1/+0Star
* | | target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu maxRichard Henderson2019-03-261-0/+5
* | | target/riscv: Fix wrong expanding for c.fswspKito Cheng2019-03-261-1/+1
* | | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc1' i...Peter Maydell2019-03-262-2/+23
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| * | | target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt2019-03-222-2/+23
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* | | Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...Peter Maydell2019-03-257-17/+17
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| * | | trace-events: Shorten file names in commentsMarkus Armbruster2019-03-227-17/+17
* | | | target/arm: make pmccntr_op_start/finish staticAndrew Jones2019-03-252-13/+2Star
* | | | target/arm: cortex-a7 and cortex-a15 have pmusAndrew Jones2019-03-251-0/+3
* | | | target/arm: fix crash on pmu register accessAndrew Jones2019-03-251-0/+4
* | | | target/arm: Fix non-parallel expansion of CASPRichard Henderson2019-03-251-1/+1
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* | | i386: Disable OSPKE on CPU model definitionsEduardo Habkost2019-03-201-3/+3
* | | i386: Make arch_capabilities migratableEduardo Habkost2019-03-201-1/+0Star
* | | i386: kvm: Disable arch_capabilities if MSR can't be setEduardo Habkost2019-03-201-0/+9
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* | target/riscv: Remove unused structAlistair Francis2019-03-191-6/+0Star
* | RISC-V: Update load reservation comment in do_interruptMichael Clark2019-03-191-1/+7
* | RISC-V: Convert trap debugging to trace eventsMichael Clark2019-03-192-9/+5Star
* | RISC-V: Add support for vectored interruptsMichael Clark2019-03-192-97/+60Star
* | RISC-V: Change local interrupts from edge to levelMichael Clark2019-03-191-2/+2
* | RISC-V: linux-user support for RVE ABIKito Cheng2019-03-192-1/+6
* | RISC-V: Allow interrupt controllers to claim interruptsMichael Clark2019-03-193-8/+15
* | riscv: pmp: Log pmp access errors as guest errorsAlistair Francis2019-03-191-7/+13
* | RISC-V: Add hooks to use the gdb xml files.Jim Wilson2019-03-193-12/+349
* | RISC-V: Add debug support for accessing CSRs.Jim Wilson2019-03-192-7/+30
* | RISC-V: Fixes to CSR_* register macros.Jim Wilson2019-03-191-2/+33
* | target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann2019-03-181-5/+25
* | target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson2019-03-151-14/+28
* | target/arm: Check access permission to ADDVL/ADDPL/RDVLAmir Charif2019-03-151-8/+14
* | target/arm: change arch timer registers access permissionDongjiu Geng2019-03-151-15/+15
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* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' i...Peter Maydell2019-03-1312-1589/+2891
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| * target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
| * target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
| * target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-133-18/+18
| * target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-132-211/+164Star
| * target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-132-71/+81
| * target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-133-30/+34
| * target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-133-100/+108
| * target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-132-11/+24
| * target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-132-16/+25
| * target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-132-60/+33Star
| * target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-132-39/+27Star
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