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* target/ppc: Set the correct endianness for powernv memory dumpsFabiano Rosas2022-01-121-1/+1
* target/ppc: Introduce a wrapper for powerpc_excpFabiano Rosas2022-01-121-1/+11
* target/ppc: Use ppc_interrupts_little_endian in powerpc_excpFabiano Rosas2022-01-121-28/+1Star
* target/ppc: Add MSR_ILE support to ppc_interrupts_little_endianFabiano Rosas2022-01-121-1/+3
* target/ppc: Add HV support to ppc_interrupts_little_endianFabiano Rosas2022-01-123-10/+17
* target/ppc: powerpc_excp: Group unimplemented exceptionsFabiano Rosas2022-01-121-69/+8Star
* target/ppc: powerpc_excp: Keep 60x/7x5 soft MMU logs activeFabiano Rosas2022-01-121-5/+1Star
* target/ppc: powerpc_excp: Extract software TLB logging into a functionFabiano Rosas2022-01-121-28/+37
* target/ppc: Add extra float instructions to POWER5P processorsCédric Le Goater2022-01-121-0/+1
* target/ppc: Add popcntb instruction to POWER5+ processorsCédric Le Goater2022-01-121-0/+1
* target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DAT...Mark Cave-Ayland2022-01-091-1/+4
* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-083-0/+8
* target/riscv: Fixup setting GVAAlistair Francis2022-01-081-15/+6Star
* target/riscv: Set the opcode in DisasContextAlistair Francis2022-01-081-0/+2
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-083-30/+175
* target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot2022-01-081-43/+158
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-084-0/+69
* target/riscv: adding high part of some csrsFrédéric Pétrot2022-01-082-0/+6
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-086-13/+295
* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-085-49/+222
* target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2022-01-084-44/+270
* target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2022-01-082-4/+25
* target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot2022-01-081-2/+19
* target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot2022-01-084-10/+163
* target/riscv: moving some insns close to similar insnsFrédéric Pétrot2022-01-081-17/+17
* target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot2022-01-083-0/+26
* target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot2022-01-084-1/+35
* target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2022-01-083-9/+36
* target/riscv: additional macros to check instruction supportFrédéric Pétrot2022-01-081-4/+16
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-0832-226/+226
* target/riscv: Fix position of 'experimental' commentPhilipp Tomsich2022-01-081-1/+2
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang2022-01-081-8/+24
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang2022-01-081-9/+25
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang2022-01-081-4/+8
* target/riscv: Enable the Hypervisor extension by defaultAlistair Francis2022-01-081-1/+1
* target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis2022-01-081-1/+1
* target/riscv/pmp: fix no pmp illegal intrsNikita Shubin2022-01-081-1/+2
* target/arm: Add missing FEAT_TLBIOS instructionsIdan Horowitz2022-01-071-0/+32
* linux-user/nios2: Map a real kuser pageRichard Henderson2022-01-061-9/+0Star
* linux-user/nios2: Properly emulate EXCP_TRAPRichard Henderson2022-01-062-2/+17
* target/sh4: Implement prctl_unalign_sigbusRichard Henderson2022-01-062-16/+38
* target/hppa: Implement prctl_unalign_sigbusRichard Henderson2022-01-062-5/+19
* target/alpha: Implement prctl_unalign_sigbusRichard Henderson2022-01-062-9/+27
* target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()Daniel Henrique Barboza2022-01-041-1/+6
* target/ppc: Use env->pnc_cyc_cntRichard Henderson2022-01-041-98/+9Star
* target/ppc: Rewrite pmu_increment_insnsRichard Henderson2022-01-041-29/+49
* target/ppc: Cache per-pmc insn and cycle count settingsRichard Henderson2022-01-046-20/+58
* target/ppc: powerpc_excp: Stop passing excp_model aroundFabiano Rosas2022-01-041-22/+21Star
* target/ppc: powerpc_excp: Move system call vectored code togetherFabiano Rosas2022-01-041-8/+5Star
* target/ppc: powerpc_excp: Set vector earlierFabiano Rosas2022-01-041-8/+8
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