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* tcg: Combine dh_is_64bit and dh_is_signed to dh_typecodeRichard Henderson2021-06-194-10/+0Star
* Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-06-174-50/+94
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| * target/i386: Added Intercept CR0 writes checkLara Lazier2021-06-161-0/+9
| * target/i386: Added consistency checks for CR0Lara Lazier2021-06-163-3/+13
| * target/i386: Added consistency checks for VMRUN intercept and ASIDLara Lazier2021-06-161-0/+10
| * target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier2021-06-162-47/+62
* | bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell2021-06-161-20/+0Star
* | target/arm: Move expand_pred_b() data to vec_helper.cPeter Maydell2021-06-163-99/+109
* | target/arm: Add framework for MVE decodePeter Maydell2021-06-165-0/+53
* | target/arm: Implement MVE LETP insnPeter Maydell2021-06-162-9/+97
* | target/arm: Implement MVE DLSTPPeter Maydell2021-06-162-5/+27
* | target/arm: Implement MVE WLSTP insnPeter Maydell2021-06-162-3/+42
* | target/arm: Implement MVE LCTPPeter Maydell2021-06-162-0/+26
* | target/arm: Let vfp_access_check() handle late NOCP checksPeter Maydell2021-06-161-5/+15
* | target/arm: Add handling for PSR.ECI/ICIPeter Maydell2021-06-165-5/+133
* | target/arm: Handle VPR semantics in existing codePeter Maydell2021-06-163-11/+57
* | target/arm: Enable FPSCR.QC bit for MVEPeter Maydell2021-06-162-10/+23
* | target/arm: Provide and use H8 and H1_8 macrosPeter Maydell2021-06-163-137/+143
* | target/arm: Fix mte page crossing testRichard Henderson2021-06-161-1/+1
* | target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16Richard Henderson2021-06-151-30/+48
* | target/arm: Remove fprintf from disas_simd_mod_immRichard Henderson2021-06-151-1/+0Star
* | target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16Richard Henderson2021-06-151-2/+2
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* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell2021-06-0813-104/+1028
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| * target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-082-0/+26
| * target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-082-0/+5
| * target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-083-0/+35
| * target/riscv: rvb: address calculationKito Cheng2021-06-083-0/+62
| * target/riscv: rvb: generalized or-combineFrank Chang2021-06-085-0/+64
| * target/riscv: rvb: generalized reverseFrank Chang2021-06-086-0/+132
| * target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-083-0/+81
| * target/riscv: rvb: shift onesKito Cheng2021-06-083-0/+74
| * target/riscv: rvb: single-bit instructionsFrank Chang2021-06-083-0/+175
| * target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-082-50/+43Star
| * target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-082-0/+15
| * target/riscv: rvb: min/max instructionsKito Cheng2021-06-082-0/+28
| * target/riscv: rvb: pack two words into one registerKito Cheng2021-06-083-0/+78
| * target/riscv: rvb: logic-with-negateKito Cheng2021-06-082-0/+21
| * target/riscv: rvb: count bits setFrank Chang2021-06-083-0/+21
| * target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-084-1/+93
| * target/riscv: reformat @sh format encoding for B-extensionKito Cheng2021-06-081-5/+5
| * target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei2021-06-081-39/+50
| * target/riscv/pmp: Add assert for ePMP operationsAlistair Francis2021-06-081-0/+4
| * target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du2021-06-081-2/+5
| * target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-082-4/+2Star
| * target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-081-0/+2
| * target/riscv: fix wfi exception behaviorJose Martins2021-06-082-3/+9
* | target/mips: Fix 'Uncoditional' typoPhilippe Mathieu-Daudé2021-06-051-3/+3
* | target/hppa: Remove unused 'memory.h' headerPhilippe Mathieu-Daudé2021-06-051-1/+0Star
* | target/nios2: fix page-fit instruction countPavel Dovgalyuk2021-06-051-1/+1
* | target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-051-0/+2
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