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* target/ppc: Add helper_mfvscrRichard Henderson2019-02-185-3/+10
* target/ppc: Remove vscr_nj and vscr_satRichard Henderson2019-02-181-2/+0Star
* target/ppc: Use helper_mtvscr for reset and gdbRichard Henderson2019-02-181-3/+2Star
* target/ppc: Pass integer to helper_mtvscrRichard Henderson2019-02-183-8/+17
* target/ppc: convert xxsel to vector operationsRichard Henderson2019-02-181-28/+27Star
* target/ppc: convert xxspltw to vector operationsRichard Henderson2019-02-181-25/+11Star
* target/ppc: convert xxspltib to vector operationsRichard Henderson2019-02-181-8/+5Star
* target/ppc: convert VSX logical operations to vector operationsRichard Henderson2019-02-181-26/+17Star
* target/ppc: convert vsplt[bhw] to use vector operationsRichard Henderson2019-02-183-41/+27Star
* target/ppc: convert vspltis[bhw] to use vector operationsRichard Henderson2019-02-183-46/+8Star
* target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector oper...Mark Cave-Ayland2019-02-183-23/+8Star
* target/ppc: convert VMX logical instructions to use vector operationsMark Cave-Ayland2019-02-182-31/+17Star
* target/ppc: Disable ISA 2.06 PM instructions on POWER9Benjamin Herrenschmidt2019-02-171-1/+1
* ppc: fix crash during branch steppingRoman Kapl2019-02-171-22/+15Star
* target/ppc: Remove some #if 0'ed codeBenjamin Herrenschmidt2019-02-172-24/+0Star
* target/ppc: Fix msync to do what hardware doesBALATON Zoltan2019-02-171-3/+8
* target/ppc: Enable reporting of SPRs to GDBFabiano Rosas2019-02-174-2/+130
* target/arm: Add missing clear_tail callsRichard Henderson2019-02-151-0/+2
* target/arm: Use vector operations for saturationRichard Henderson2019-02-155-44/+331
* target/arm: Split out FPSCR.QC to a vector fieldRichard Henderson2019-02-154-7/+21
* target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]Richard Henderson2019-02-151-7/+8
* target/arm: Split out flags setting from vfp comparesRichard Henderson2019-02-151-18/+27
* target/arm: Fix arm_cpu_dump_state vs FPSCRRichard Henderson2019-02-151-1/+1
* target/arm: Fix vfp_gdb_get/set_reg vs FPSCRRichard Henderson2019-02-151-2/+2
* target/arm: Remove neon min/max helpersRichard Henderson2019-02-152-24/+0Star
* target/arm: Use tcg integer min/max primitives for neonRichard Henderson2019-02-151-4/+4
* target/arm: Use vector minmax expanders for aarch32Richard Henderson2019-02-151-6/+19
* target/arm: Use vector minmax expanders for aarch64Richard Henderson2019-02-151-21/+14Star
* target/arm: Rely on optimization within tcg_gen_gvec_orRichard Henderson2019-02-153-19/+5Star
* arm: Allow system registers for KVM guests to be changed by QEMU codePeter Maydell2019-02-155-22/+38
* target/arm: expose remaining CPUID registers as RAZAlex Bennée2019-02-152-3/+26
* target/arm: expose MPIDR_EL1 to userspaceAlex Bennée2019-02-151-7/+14
* target/arm: expose CPUID registers to userspaceAlex Bennée2019-02-152-0/+80
* target/arm: relax permission checks for HWCAP_CPUID registersAlex Bennée2019-02-152-1/+17
* target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_beCatherine Ho2019-02-151-2/+2
* target/arm: Implement HACR_EL2Peter Maydell2019-02-151-0/+6
* target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTRAaron Lindsay OS2019-02-151-4/+4
* target/mips: introduce MTTCG-enabled buildsAleksandar Markovic2019-02-141-0/+2
* target/mips: hold BQL in mips_vpe_wake()Goran Ferenc2019-02-141-0/+3
* hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic2019-02-141-18/+3Star
* target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae2019-02-145-118/+44Star
* target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae2019-02-144-18/+25
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf1' i...Peter Maydell2019-02-148-106/+394
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| * target/riscv: fix counter-enable checks in ctr()Xi Wang2019-02-121-3/+9
| * RISC-V: Add misa runtime write supportMichael Clark2019-02-124-3/+68
| * RISC-V: Add misa.MAFD checks to translateMichael Clark2019-02-121-0/+158
| * RISC-V: Add misa to DisasContextMichael Clark2019-02-121-35/+40
| * RISC-V: Add priv_ver to DisasContextAlistair Francis2019-02-121-2/+5
| * RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-125-37/+36Star
| * RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark2019-02-122-8/+34
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