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* Merge tag 'pull-target-arm-20221010' of https://git.linaro.org/people/pmaydel...Stefan Hajnoczi2022-10-1210-584/+710
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| * target/arm: Use ARMGranuleSize in ARMVAParametersPeter Maydell2022-10-103-20/+50
| * target/arm: Don't allow guest to use unimplemented granule sizesPeter Maydell2022-10-103-8/+136
| * target/arm: Use tlb_set_page_fullRichard Henderson2022-10-105-114/+111Star
| * target/arm: Fix cacheattr in get_phys_addr_disabledRichard Henderson2022-10-101-23/+25
| * target/arm: Split out get_phys_addr_disabledRichard Henderson2022-10-101-64/+74
| * target/arm: Fix ATS12NSO* from S PL1Richard Henderson2022-10-101-4/+4
| * target/arm: Pass HCR to attribute subroutines.Richard Henderson2022-10-101-13/+17
| * target/arm: Remove env argument from combined_attrs_fwbRichard Henderson2022-10-101-3/+2Star
| * target/arm: Hoist read of *is_secure in S1_ptw_translateRichard Henderson2022-10-101-10/+12
| * target/arm: Introduce arm_hcr_el2_eff_secstateRichard Henderson2022-10-102-10/+21
| * target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.MRichard Henderson2022-10-101-2/+2
| * target/arm: Reorg regime_translation_disabledRichard Henderson2022-10-101-7/+25
| * target/arm: Fold secure and non-secure a-profile mmu indexesRichard Henderson2022-10-107-203/+85Star
| * target/arm: Add is_secure parameter to do_ats_writeRichard Henderson2022-10-101-5/+14
| * target/arm: Merge regime_is_secure into get_phys_addrRichard Henderson2022-10-102-44/+42Star
| * target/arm: Add TBFLAG_M32.SECURERichard Henderson2022-10-103-2/+7
| * target/arm: Add is_secure parameter to v7m_read_half_insnRichard Henderson2022-10-101-5/+4Star
| * target/arm: Split out get_phys_addr_with_secureRichard Henderson2022-10-102-29/+55
| * target/arm: Add is_secure parameter to regime_translation_disabledRichard Henderson2022-10-101-9/+11
| * target/arm: Fix S2 disabled check in S1_ptw_translateRichard Henderson2022-10-101-3/+3
| * target/arm: Add is_secure parameter to get_phys_addr_lpaeRichard Henderson2022-10-101-10/+10
| * target/arm: Make the final stage1+2 write to secure be unconditionalRichard Henderson2022-10-101-11/+10Star
| * target/arm: Split s2walk_secure from ipa_secure in get_phys_addrRichard Henderson2022-10-101-9/+9
| * target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implementedJerome Forissier2022-10-102-28/+31
| * target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTRPeter Maydell2022-10-101-1/+3
* | dump: Replace opaque DumpState pointer with a typed oneJanosch Frank2022-10-0610-48/+44Star
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* monitor: expose monitor_puts to rest of codeAlex Bennée2022-10-061-1/+1
* Merge tag 'pull-hex-20221003' of https://github.com/quic/qemu into stagingStefan Hajnoczi2022-10-059-137/+192
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| * Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEWMatheus Tavares Bernardino2022-10-031-1/+1
| * Hexagon (target/hexagon) move store size tracking to translationTaylor Simpson2022-09-303-28/+41
| * Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]Taylor Simpson2022-09-304-10/+17
| * Hexagon (target/hexagon) add instruction attributes from archlibTaylor Simpson2022-09-303-98/+133
* | Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2022-10-0531-107/+298
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| * | target/sh4: Fix TB_FLAG_UNALIGNRichard Henderson2022-10-044-74/+86
| * | accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-0415-19/+19
| * | hw/core: Add CPUClass.get_pcRichard Henderson2022-10-0421-0/+183
| * | accel/tcg: Suppress auto-invalidate in probe_access_internalRichard Henderson2022-10-041-4/+0Star
| * | accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFullRichard Henderson2022-10-043-10/+10
* | | Merge tag 'trivial-branch-for-7.2-pull-request' of https://gitlab.com/laurent...Stefan Hajnoczi2022-10-042-16/+10Star
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| * | | Drop superfluous conditionals around g_free()Markus Armbruster2022-10-042-16/+10Star
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* | | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2022-10-041-1/+1
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| * | target/i386/kvm: fix kvmclock_current_nsec: Assertion `time.tsc_timestamp <= ...Ray Zhang2022-10-011-1/+1
* | | target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEPJerome Forissier2022-09-291-1/+1
* | | target/arm: Rearrange cpu64.c so all the CPU initfns are togetherPeter Maydell2022-09-291-356/+356
* | | target/arm: Update SDCR_VALID_MASK to include SCCDPeter Maydell2022-09-291-1/+7
* | | target/arm: Make writes to MDCR_EL3 use PMU start/finish callsPeter Maydell2022-09-291-4/+14
* | | target/arm: Mark registers which call pmu_op_start() as ARM_CP_IOPeter Maydell2022-09-291-6/+6
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* | Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_viv...Stefan Hajnoczi2022-09-281-2/+4
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| * | linux-user/hppa: Dump IIR on register dumpHelge Deller2022-09-271-2/+4
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