| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Enable SVE2 and related extensions | Richard Henderson | 2021-05-25 | 3 | -0/+16 |
| * | target/arm: Implement integer matrix multiply accumulate | Richard Henderson | 2021-05-25 | 7 | -0/+169 |
| * | target/arm: Implement aarch32 VSUDOT, VUSDOT | Richard Henderson | 2021-05-25 | 3 | -0/+38 |
| * | target/arm: Split decode of VSDOT and VUDOT | Richard Henderson | 2021-05-25 | 2 | -11/+28 |
| * | target/arm: Split out do_neon_ddda | Richard Henderson | 2021-05-25 | 1 | -52/+38 |
| * | target/arm: Fix decode for VDOT (indexed) | Richard Henderson | 2021-05-25 | 2 | -3/+3 |
| * | target/arm: Remove unused fpst from VDOT_scalar | Richard Henderson | 2021-05-25 | 1 | -3/+0 |
| * | target/arm: Split out do_neon_ddda_fpst | Richard Henderson | 2021-05-25 | 1 | -55/+43 |
| * | target/arm: Implement aarch64 SUDOT, USDOT | Richard Henderson | 2021-05-25 | 2 | -0/+30 |
| * | target/arm: Implement SVE2 fp multiply-add long | Stephen Long | 2021-05-25 | 4 | -0/+141 |
| * | target/arm: Move endian adjustment macros to vec_internal.h | Richard Henderson | 2021-05-25 | 3 | -28/+24 |
| * | target/arm: Implement SVE2 bitwise shift immediate | Stephen Long | 2021-05-25 | 4 | -0/+133 |
| * | target/arm: Implement 128-bit ZIP, UZP, TRN | Richard Henderson | 2021-05-25 | 4 | -8/+90 |
| * | target/arm: Implement SVE2 LD1RO | Richard Henderson | 2021-05-25 | 2 | -0/+97 |
| * | target/arm: Tidy do_ldrq | Richard Henderson | 2021-05-25 | 1 | -9/+4 |
| * | target/arm: Share table of sve load functions | Richard Henderson | 2021-05-25 | 1 | -128/+126 |
| * | target/arm: Implement SVE2 FLOGB | Stephen Long | 2021-05-25 | 4 | -0/+119 |
| * | target/arm: Implement SVE2 FCVTXNT, FCVTX | Stephen Long | 2021-05-25 | 2 | -10/+41 |
| * | target/arm: Implement SVE2 FCVTLT | Stephen Long | 2021-05-25 | 4 | -0/+46 |
| * | target/arm: Implement SVE2 FCVTNT | Richard Henderson | 2021-05-25 | 4 | -0/+45 |
| * | target/arm: Implement SVE2 TBL, TBX | Stephen Long | 2021-05-25 | 4 | -19/+119 |
| * | target/arm: Implement SVE2 crypto constructive binary operations | Richard Henderson | 2021-05-25 | 3 | -0/+25 |
| * | target/arm: Implement SVE2 crypto destructive binary operations | Richard Henderson | 2021-05-25 | 3 | -0/+50 |
| * | target/arm: Implement SVE2 crypto unary operations | Richard Henderson | 2021-05-25 | 2 | -0/+17 |
| * | target/arm: Implement SVE mixed sign dot product | Richard Henderson | 2021-05-25 | 4 | -0/+22 |
| * | target/arm: Implement SVE mixed sign dot product (indexed) | Richard Henderson | 2021-05-25 | 5 | -0/+31 |
| * | target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h} | Richard Henderson | 2021-05-25 | 1 | -131/+29 |
| * | target/arm: Macroize helper_gvec_{s,u}dot_{b,h} | Richard Henderson | 2021-05-25 | 1 | -64/+22 |
| * | target/arm: Implement SVE2 complex integer dot product | Richard Henderson | 2021-05-25 | 4 | -0/+135 |
| * | target/arm: Implement SVE2 complex integer multiply-add (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+64 |
| * | target/arm: Implement SVE2 integer multiply long (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+31 |
| * | target/arm: Implement SVE2 multiply-add long (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+71 |
| * | target/arm: Implement SVE2 saturating multiply high (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+118 |
| * | target/arm: Implement SVE2 signed saturating doubling multiply high | Richard Henderson | 2021-05-25 | 4 | -0/+116 |
| * | target/arm: Implement SVE2 saturating multiply (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+51 |
| * | target/arm: Implement SVE2 saturating multiply-add (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+76 |
| * | target/arm: Implement SVE2 saturating multiply-add high (indexed) | Richard Henderson | 2021-05-25 | 4 | -0/+66 |
| * | target/arm: Implement SVE2 integer multiply-add (indexed) | Richard Henderson | 2021-05-25 | 2 | -0/+39 |
| * | target/arm: Implement SVE2 integer multiply (indexed) | Richard Henderson | 2021-05-25 | 2 | -0/+37 |
| * | target/arm: Split out formats for 3 vectors + 1 index | Richard Henderson | 2021-05-25 | 2 | -20/+47 |
| * | target/arm: Split out formats for 2 vectors + 1 index | Richard Henderson | 2021-05-25 | 1 | -4/+10 |
| * | target/arm: Pass separate addend to FCMLA helpers | Richard Henderson | 2021-05-25 | 5 | -51/+62 |
| * | target/arm: Pass separate addend to {U, S}DOT helpers | Richard Henderson | 2021-05-25 | 6 | -77/+110 |
| * | target/arm: Use correct output type for gvec_sdot_*_b | Richard Henderson | 2021-05-25 | 1 | -4/+4 |
| * | target/arm: Implement SVE2 SPLICE, EXT | Stephen Long | 2021-05-25 | 2 | -7/+39 |
| * | target/arm: Implement SVE2 FMMLA | Stephen Long | 2021-05-25 | 5 | -0/+125 |
| * | target/arm: Implement SVE2 gather load insns | Stephen Long | 2021-05-25 | 2 | -0/+19 |
| * | target/arm: Implement SVE2 scatter store insns | Stephen Long | 2021-05-25 | 2 | -0/+18 |
| * | target/arm: Implement SVE2 XAR | Richard Henderson | 2021-05-25 | 8 | -21/+172 |
| * | target/arm: Implement SVE2 HISTCNT, HISTSEG | Stephen Long | 2021-05-25 | 4 | -0/+163 |
