bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/arm: don't bother with id_aa64pfr0_read for USER_ONLY	Alex Bennée	2020-03-17	1	-5/+15
*	target/arm: generate xml description of our SVE registers	Alex Bennée	2020-03-17	3	-5/+261
*	target/arm: default SVE length to 64 bytes for linux-user	Alex Bennée	2020-03-17	1	-3/+4
*	target/arm: explicitly encode regnum in our XML	Alex Bennée	2020-03-17	3	-8/+13
*	target/arm: prepare for multiple dynamic XMLs	Alex Bennée	2020-03-17	3	-24/+30
*	gdbstub: extend GByteArray to read register helpers	Alex Bennée	2020-03-17	37	-119/+126
*	target/i386: use gdb_get_reg helpers	Alex Bennée	2020-03-17	1	-16/+11
*	target/m68k: use gdb_get_reg helpers	Alex Bennée	2020-03-17	1	-18/+11
*	target/arm: use gdb_get_reg helpers	Alex Bennée	2020-03-17	1	-11/+7
*	target/riscv: Fix VS mode interrupts forwarding.	Rajnesh Kanwal	2020-03-17	1	-1/+8
*	target/riscv: Correctly implement TSR trap	Alistair Francis	2020-03-17	1	-1/+1
*	target/arm: kvm: Inject events at the last stage of sync	Beata Michalska	2020-03-12	2	-10/+20
*	target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap	Eric Auger	2020-03-12	2	-6/+11
*	target/arm: Disable clean_data_tbi for system mode	Richard Henderson	2020-03-12	1	-0/+11
*	target/arm: Check addresses for disabled regimes	Richard Henderson	2020-03-12	1	-1/+34
*	target/arm: Fix some comment typos	Peter Maydell	2020-03-12	2	-2/+2
*	target/arm: Recalculate hflags correctly after writes to CONTROL	Peter Maydell	2020-03-12	3	-4/+16
*	target/arm: Update hflags in trans_CPS_v7m()	Peter Maydell	2020-03-12	1	-1/+4
*	s390x: ipl: Consolidate iplb validity check into one function	Janosch Frank	2020-03-10	1	-1/+1
*	RISC-V: Add a missing "," in riscv_excp_names	Palmer Dabbelt	2020-03-05	1	-2/+2
*	target/arm: Clean address for DC ZVA	Richard Henderson	2020-03-05	1	-1/+1
*	target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva	Richard Henderson	2020-03-05	1	-1/+1
*	target/arm: Move helper_dc_zva to helper-a64.c	Richard Henderson	2020-03-05	4	-94/+92
*	target/arm: Apply TBI to ESR_ELx in helper_exception_return	Richard Henderson	2020-03-05	1	-1/+22
*	target/arm: Introduce core_to_aa64_mmu_idx	Richard Henderson	2020-03-05	2	-1/+7
*	target/arm: Optimize cpu_mmu_index	Richard Henderson	2020-03-05	2	-15/+13
*	target/arm: Replicate TBI/TBID bits for single range regimes	Richard Henderson	2020-03-05	1	-2/+4
*	target/arm: Honor the HCR_EL2.TTLB bit	Richard Henderson	2020-03-05	1	-30/+55
*	target/arm: Honor the HCR_EL2.TPU bit	Richard Henderson	2020-03-05	1	-20/+31
*	target/arm: Honor the HCR_EL2.TPCP bit	Richard Henderson	2020-03-05	1	-8/+31
*	target/arm: Honor the HCR_EL2.TACR bit	Richard Henderson	2020-03-05	1	-4/+14
*	target/arm: Honor the HCR_EL2.TSW bit	Richard Henderson	2020-03-05	1	-6/+16
*	target/arm: Honor the HCR_EL2.{TVM,TRVM} bits	Richard Henderson	2020-03-05	1	-27/+55
*	target/arm: Improve masking in arm_hcr_el2_eff	Richard Henderson	2020-03-05	1	-4/+27
*	target/arm: Remove EL2 and EL3 setup from user-only	Richard Henderson	2020-03-05	1	-6/+0
*	target/arm: Disable has_el2 and has_el3 for user-only	Richard Henderson	2020-03-05	1	-2/+4
*	target/arm: Add HCR_EL2 bit definitions from ARMv8.6	Richard Henderson	2020-03-05	1	-0/+7
*	target/arm: Improve masking of HCR/HCR2 RES0 bits	Richard Henderson	2020-03-05	1	-13/+25
*	target/arm: Implement (trivially) ARMv8.2-TTCNP	Peter Maydell	2020-03-05	3	-0/+7
*	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...	Peter Maydell	2020-03-03	10	-133/+1223
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\| *	target/riscv: Emulate TIME CSRs for privileged mode	Anup Patel	2020-02-27	3	-4/+92
\| *	target/riscv: Allow enabling the Hypervisor extension	Alistair Francis	2020-02-27	2	-0/+6
\| *	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	Alistair Francis	2020-02-27	4	-4/+15
\| *	target/riscv: Add support for the 32-bit MSTATUSH CSR	Alistair Francis	2020-02-27	6	-0/+62
\| *	target/riscv: Set htval and mtval2 on execptions	Alistair Francis	2020-02-27	1	-0/+10
\| *	target/riscv: Raise the new execptions when 2nd stage translation fails	Alistair Francis	2020-02-27	1	-6/+18
\| *	target/riscv: Implement second stage MMU	Alistair Francis	2020-02-27	2	-19/+175
\| *	target/riscv: Allow specifying MMU stage	Alistair Francis	2020-02-27	1	-9/+28
\| *	target/riscv: Respect MPRV and SPRV for floating point ops	Alistair Francis	2020-02-27	1	-1/+15
\| *	target/riscv: Mark both sstatus and msstatus_hs as dirty	Alistair Francis	2020-02-27	1	-0/+13