bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/ppc: Validate hflags with CONFIG_DEBUG_TCG	Richard Henderson	2021-05-04	2	-2/+32
*	target/ppc: Remove env->immu_idx and env->dmmu_idx	Richard Henderson	2021-05-04	6	-56/+56
*	target/ppc: Remove MSR_SA and MSR_AP from hflags	Richard Henderson	2021-05-04	2	-9/+5
*	target/ppc: Put LPCR[GTSE] in hflags	Richard Henderson	2021-05-04	4	-1/+8
*	target/ppc: Create helper_scv	Richard Henderson	2021-05-04	3	-13/+17
*	target/ppc: Put dbcr0 single-step bits into hflags	Richard Henderson	2021-05-04	3	-18/+20
*	target/ppc: Reduce env->hflags to uint32_t	Richard Henderson	2021-05-04	3	-4/+4
*	target/ppc: Disconnect hflags from MSR	Richard Henderson	2021-05-04	3	-50/+95
*	target/ppc: Extract post_load_update_msr	Richard Henderson	2021-05-04	1	-16/+14
*	target/ppc: Fix comment for MSR_FE{0,1}	Richard Henderson	2021-05-04	1	-2/+2
*	target/ppc: Retain hflags_nmsr only for migration	Richard Henderson	2021-05-04	3	-7/+8
*	target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr	Richard Henderson	2021-05-04	1	-6/+1
*	target/ppc: Properly sync cpu state with new msr in cpu_load_old	Richard Henderson	2021-05-04	1	-2/+11
*	target/ppc: Move 601 hflags adjustment to hreg_compute_hflags	Richard Henderson	2021-05-04	4	-9/+18
*	target/ppc: Move helper_regs.h functions out-of-line	Richard Henderson	2021-05-04	4	-176/+207
*	Hexagon (target/hexagon) CABAC decode bin	Taylor Simpson	2021-05-02	6	-0/+165
*	Hexagon (target/hexagon) load into shifted register instructions	Taylor Simpson	2021-05-02	3	-0/+88
*	Hexagon (target/hexagon) load and unpack bytes instructions	Taylor Simpson	2021-05-02	5	-0/+186
*	Hexagon (target/hexagon) bit reverse (brev) addressing	Taylor Simpson	2021-05-02	7	-0/+50
*	Hexagon (target/hexagon) circular addressing	Taylor Simpson	2021-05-02	7	-23/+346
*	Hexagon (target/hexagon) add A4_addp_c/A4_subp_c	Taylor Simpson	2021-05-01	4	-0/+65
*	Hexagon (target/hexagon) add A6_vminub_RdP	Taylor Simpson	2021-05-01	4	-0/+60
*	Hexagon (target/hexagon) add A5_ACS (vacsh)	Taylor Simpson	2021-05-01	5	-0/+60
*	Hexagon (target/hexagon) add F2_sfinvsqrta	Taylor Simpson	2021-05-01	7	-1/+77
*	Hexagon (target/hexagon) add F2_sfrecipa instruction	Taylor Simpson	2021-05-01	7	-3/+101
*	Hexagon (target/hexagon) compile all debug code	Taylor Simpson	2021-05-01	6	-94/+81
*	Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h	Taylor Simpson	2021-05-01	1	-1/+2
*	Hexagon (target/hexagon) cleanup reg_field_info definition	Taylor Simpson	2021-05-01	2	-4/+3
*	Hexagon (target/hexagon) cleanup ternary operators in semantics	Taylor Simpson	2021-05-01	1	-6/+6
*	Hexagon (target/hexagon) use softfloat for float-to-int conversions	Taylor Simpson	2021-05-01	6	-259/+136
*	Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn	Taylor Simpson	2021-05-01	1	-17/+11
*	Hexagon (target/hexagon) use softfloat default NaN and tininess	Taylor Simpson	2021-05-01	2	-47/+5
*	Hexagon (target/hexagon) change type of softfloat_roundingmodes	Taylor Simpson	2021-05-01	1	-1/+1
*	Hexagon (target/hexagon) remove unused carry_from_add64 function	Taylor Simpson	2021-05-01	3	-16/+0
*	Hexagon (target/hexagon) change variables from int to bool when appropriate	Taylor Simpson	2021-05-01	6	-59/+60
*	Hexagon (target/hexagon) decide if pred has been written at TCG gen time	Taylor Simpson	2021-05-01	4	-10/+25
*	Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN	Taylor Simpson	2021-05-01	2	-32/+33
*	Hexagon (target/hexagon) use env_archcpu and env_cpu	Taylor Simpson	2021-05-01	4	-9/+4
*	Hexagon (target/hexagon) remove unnecessary inline directives	Taylor Simpson	2021-05-01	5	-47/+46
*	Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair	Taylor Simpson	2021-05-01	1	-14/+13
*	Hexagon (target/hexagon) TCG generation cleanup	Taylor Simpson	2021-05-01	1	-5/+9
*	target/hexagon: remove unnecessary semicolons	Taylor Simpson	2021-05-01	1	-2/+2
*	target/hexagon: fix typo in comment	Taylor Simpson	2021-05-01	1	-1/+1
*	target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM	Taylor Simpson	2021-05-01	1	-2/+2
*	target/hexagon: remove unnecessary checks in find_iclass_slots	Taylor Simpson	2021-05-01	1	-4/+0
*	target/hexagon: translation changes	Taylor Simpson	2021-05-01	1	-17/+9
*	target/arm: Enforce alignment for sve LD1R	Richard Henderson	2021-04-30	1	-1/+1
*	target/arm: Enforce alignment for aa64 vector LDn/STn (single)	Richard Henderson	2021-04-30	1	-4/+5
*	target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)	Richard Henderson	2021-04-30	1	-4/+11
*	target/arm: Use MemOp for size + endian in aa64 vector ld/st	Richard Henderson	2021-04-30	1	-10/+10