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* target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont2021-01-191-13/+18
* target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont2021-01-193-29/+16Star
* target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont2021-01-191-0/+17
* target/arm: remove redundant testsRémi Denis-Courmont2021-01-192-10/+8Star
* target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson2021-01-191-14/+10Star
* target/arm: Add cpu properties to control pauthRichard Henderson2021-01-194-4/+60
* target/arm: Implement an IMPDEF pauth algorithmRichard Henderson2021-01-192-9/+33
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell2021-01-1812-1184/+99Star
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| * riscv: Add semihosting supportKeith Packard2021-01-184-1/+58
| * semihosting: Change common-semi API to be architecture-independentKeith Packard2021-01-183-11/+9Star
| * semihosting: Move ARM semihosting code to shared directoriesKeith Packard2021-01-182-1123/+0Star
| * target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée2021-01-182-47/+30Star
| * gdbstub: drop CPUEnv from gdb_exit()Alex Bennée2021-01-183-3/+3
* | target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-163-264/+58Star
* | target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-162-84/+249
* | target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-162-9/+9
* | target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-163-2/+8
* | gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
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* target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2021-01-142-10/+7Star
* target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2021-01-142-5/+2Star
* target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé2021-01-141-1/+0Star
* target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+2
* target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
* target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+8
* target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+5
* target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-4/+6
* target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé2021-01-142-2/+3
* target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé2021-01-142-1/+2
* target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé2021-01-143-2/+9
* target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé2021-01-141-23/+5Star
* target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-146-0/+80
* target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-144-0/+37
* target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé2021-01-144-32/+71
* target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé2021-01-143-62/+11Star
* target/mips: Introduce decode tree bindings for MSA ASEPhilippe Mathieu-Daudé2021-01-144-0/+68
* target/mips: Pass TCGCond argument to MSA gen_check_zero_element()Philippe Mathieu-Daudé2021-01-141-6/+4Star
* target/mips: Extract MSA translation routinesPhilippe Mathieu-Daudé2021-01-143-2249/+2266
* target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé2021-01-142-2/+4
* target/mips: Extract MSA helper definitionsPhilippe Mathieu-Daudé2021-01-142-434/+445
* target/mips: Extract MSA helpers from op_helper.cPhilippe Mathieu-Daudé2021-01-142-394/+393Star
* target/mips: Move msa_reset() to msa_helper.cPhilippe Mathieu-Daudé2021-01-144-36/+39
* target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()Philippe Mathieu-Daudé2021-01-141-21/+48
* target/mips: Remove CPUMIPSState* argument from gen_msa*() methodsPhilippe Mathieu-Daudé2021-01-141-29/+28Star
* target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé2021-01-142-13/+21
* target/mips: Alias MSA vector registers on FPU scalar registersPhilippe Mathieu-Daudé2021-01-141-5/+9
* target/mips: Remove now unused ASE_MSA definitionPhilippe Mathieu-Daudé2021-01-142-5/+4Star
* target/mips: Simplify MSA TCG logicPhilippe Mathieu-Daudé2021-01-141-12/+11Star
* target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSAPhilippe Mathieu-Daudé2021-01-141-1/+1
* target/mips: Simplify msa_reset()Philippe Mathieu-Daudé2021-01-142-4/+5
* target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé2021-01-144-11/+15
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