| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Enable TARGET_TB_PCREL | Richard Henderson | 2022-10-20 | 6 | -71/+178 |
| * | target/arm: Introduce gen_pc_plus_diff for aarch32 | Richard Henderson | 2022-10-20 | 1 | -17/+21 |
| * | target/arm: Introduce gen_pc_plus_diff for aarch64 | Richard Henderson | 2022-10-20 | 1 | -12/+29 |
| * | target/arm: Change gen_jmp* to work on displacements | Richard Henderson | 2022-10-20 | 1 | -16/+21 |
| * | target/arm: Remove gen_exception_internal_insn pc argument | Richard Henderson | 2022-10-20 | 2 | -8/+8 |
| * | target/arm: Change gen_exception_insn* to work on displacements | Richard Henderson | 2022-10-20 | 6 | -46/+43 |
| * | target/arm: Change gen_*set_pc_im to gen_*update_pc | Richard Henderson | 2022-10-20 | 5 | -54/+56 |
| * | target/arm: Change gen_goto_tb to work on displacements | Richard Henderson | 2022-10-20 | 2 | -23/+27 |
| * | target/arm: Introduce curr_insn_len | Richard Henderson | 2022-10-20 | 3 | -4/+8 |
| * | target/arm: Use bool consistently for get_phys_addr subroutines | Richard Henderson | 2022-10-20 | 1 | -4/+3 |
| * | target/arm: Split out get_phys_addr_twostage | Richard Henderson | 2022-10-20 | 1 | -91/+100 |
| * | target/arm: Use softmmu tlbs for page table walking | Richard Henderson | 2022-10-20 | 3 | -75/+145 |
| * | target/arm: Move be test for regime into S1TranslateResult | Richard Henderson | 2022-10-20 | 1 | -2/+4 |
| * | target/arm: Plumb debug into S1Translate | Richard Henderson | 2022-10-20 | 1 | -18/+37 |
| * | target/arm: Split out S1Translate type | Richard Henderson | 2022-10-20 | 1 | -61/+79 |
| * | target/arm: Restrict tlb flush from vttbr_write to vmid change | Richard Henderson | 2022-10-20 | 1 | -2/+2 |
| * | target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx | Richard Henderson | 2022-10-20 | 3 | -49/+127 |
| * | target/arm: Add ARMMMUIdx_Phys_{S,NS} | Richard Henderson | 2022-10-20 | 3 | -4/+24 |
| * | target/arm: Use probe_access_full for BTI | Richard Henderson | 2022-10-20 | 5 | -31/+20 |
| * | target/arm: Use probe_access_full for MTE | Richard Henderson | 2022-10-20 | 5 | -86/+36 |
| * | target/arm: Enable TARGET_PAGE_ENTRY_EXTRA | Richard Henderson | 2022-10-20 | 2 | -0/+15 |
| * | target/arm: update the cortex-a15 MIDR to latest rev | Alex Bennée | 2022-10-20 | 1 | -1/+3 |
| * | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Stefan Hajnoczi | 2022-10-18 | 17 | -2795/+5795 |
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| | * | target/i386: remove old SSE decoder | Paolo Bonzini | 2022-10-18 | 5 | -1907/+19 |
| | * | target/i386: move 3DNow to the new decoder | Paolo Bonzini | 2022-10-18 | 6 | -76/+74 |
| | * | target/i386: Enable AVX cpuid bits when using TCG | Paul Brook | 2022-10-18 | 1 | -5/+5 |
| | * | target/i386: implement VLDMXCSR/VSTMXCSR | Paolo Bonzini | 2022-10-18 | 2 | -0/+45 |
| | * | target/i386: implement XSAVE and XRSTOR of AVX registers | Paolo Bonzini | 2022-10-18 | 1 | -3/+75 |
| | * | target/i386: reimplement 0x0f 0x28-0x2f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+185 |
| | * | target/i386: reimplement 0x0f 0x10-0x17, add AVX | Paolo Bonzini | 2022-10-18 | 5 | -0/+264 |
| | * | target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+81 |
| | * | target/i386: reimplement 0x0f 0x38, add AVX | Paolo Bonzini | 2022-10-18 | 6 | -8/+524 |
| | * | target/i386: Use tcg gvec ops for pmovmskb | Richard Henderson | 2022-10-18 | 1 | -5/+83 |
| | * | target/i386: reimplement 0x0f 0x3a, add AVX | Paolo Bonzini | 2022-10-18 | 5 | -1/+491 |
| | * | target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes | Paolo Bonzini | 2022-10-18 | 2 | -5/+5 |
| | * | target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX | Paolo Bonzini | 2022-10-18 | 4 | -11/+122 |
| | * | target/i386: reimplement 0x0f 0x70-0x77, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -6/+293 |
| | * | target/i386: reimplement 0x0f 0x78-0x7f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+138 |
| | * | target/i386: reimplement 0x0f 0x50-0x5f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+210 |
| | * | target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+63 |
| | * | target/i386: reimplement 0x0f 0x60-0x6f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+262 |
| | * | target/i386: Introduce 256-bit vector helpers | Paolo Bonzini | 2022-10-18 | 4 | -0/+14 |
| | * | target/i386: implement additional AVX comparison operators | Paolo Bonzini | 2022-10-18 | 2 | -0/+65 |
| | * | target/i386: provide 3-operand versions of unary scalar helpers | Paolo Bonzini | 2022-10-18 | 3 | -25/+61 |
| | * | target/i386: support operand merging in binary scalar helpers | Paolo Bonzini | 2022-10-18 | 1 | -0/+16 |
| | * | target/i386: extend helpers to support VEX.V 3- and 4- operand encodings | Paolo Bonzini | 2022-10-18 | 3 | -238/+265 |
| | * | target/i386: Prepare ops_sse_header.h for 256 bit AVX | Paul Brook | 2022-10-18 | 1 | -40/+76 |
| | * | target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder | Paolo Bonzini | 2022-10-18 | 3 | -289/+321 |
| | * | target/i386: validate SSE prefixes directly in the decoding table | Paolo Bonzini | 2022-10-18 | 2 | -0/+38 |
| | * | target/i386: validate VEX prefixes via the instructions' exception classes | Paolo Bonzini | 2022-10-18 | 4 | -12/+239 |
