| Commit message (Expand) | Author | Age | Files | Lines |
* | linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI | Richard Henderson | 2020-10-27 | 2 | -2/+7 |
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20201026' into staging | Peter Maydell | 2020-10-26 | 4 | -2/+14 |
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| * | s390x: pv: Fix diag318 PV fencing | Janosch Frank | 2020-10-22 | 4 | -2/+14 |
* | | target/riscv: raise exception to HS-mode at get_physical_address | Yifei Jiang | 2020-10-22 | 2 | -12/+34 |
* | | target/riscv: Fix implementation of HLVX.WU instruction | Georg Kotheimer | 2020-10-22 | 1 | -3/+3 |
* | | target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt | Georg Kotheimer | 2020-10-22 | 1 | -1/+3 |
* | | target/riscv: Fix update of hstatus.SPVP | Georg Kotheimer | 2020-10-22 | 1 | -1/+1 |
* | | riscv: Convert interrupt logs to use qemu_log_mask() | Alistair Francis | 2020-10-22 | 2 | -2/+7 |
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* | target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension | Peter Maydell | 2020-10-20 | 3 | -0/+16 |
* | target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 | Peter Maydell | 2020-10-20 | 1 | -19/+28 |
* | target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile | Peter Maydell | 2020-10-20 | 1 | -12/+19 |
* | target/arm: Implement v8.1M low-overhead-loop instructions | Peter Maydell | 2020-10-20 | 2 | -2/+99 |
* | target/arm: Implement v8.1M branch-future insns (as NOPs) | Peter Maydell | 2020-10-20 | 3 | -1/+38 |
* | target/arm: Don't allow BLX imm for M-profile | Peter Maydell | 2020-10-20 | 1 | -0/+8 |
* | target/arm: Make the t32 insn[25:23]=111 group non-overlapping | Peter Maydell | 2020-10-20 | 1 | -13/+11 |
* | target/arm: Implement v8.1M conditional-select insns | Peter Maydell | 2020-10-20 | 2 | -0/+63 |
* | target/arm: Implement v8.1M NOCP handling | Peter Maydell | 2020-10-20 | 3 | -6/+22 |
* | target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11 | Richard Henderson | 2020-10-20 | 2 | -8/+10 |
* | target/arm: Fix reported EL for mte_check_fail | Richard Henderson | 2020-10-20 | 1 | -7/+3 |
* | target/arm: Remove redundant mmu_idx lookup | Richard Henderson | 2020-10-20 | 1 | -2/+1 |
* | target/arm: Use tlb_flush_page_bits_by_mmuidx* | Richard Henderson | 2020-10-20 | 1 | -7/+39 |
* | target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest | Peter Maydell | 2020-10-20 | 3 | -13/+47 |
* | target/arm: Fix SMLAD incorrect setting of Q bit | Peter Maydell | 2020-10-20 | 1 | -11/+49 |
* | Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' ... | Peter Maydell | 2020-10-19 | 9 | -109/+756 |
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| * | target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -1/+1 |
| * | target/mips/cpu: Display warning when CPU is used without input clock | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -0/+10 |
| * | target/mips/cpu: Introduce mips_cpu_create_with_clock() helper | Philippe Mathieu-Daudé | 2020-10-17 | 2 | -0/+24 |
| * | target/mips/cpu: Allow the CPU to use dynamic frequencies | Philippe Mathieu-Daudé | 2020-10-17 | 2 | -2/+13 |
| * | target/mips/cpu: Make cp0_count_rate a property | Philippe Mathieu-Daudé | 2020-10-17 | 2 | -8/+20 |
| * | target/mips/cpu: Calculate the CP0 timer period using the CPU frequency | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -2/+2 |
| * | target/mips: Move cp0_count_ns to CPUMIPSState | Philippe Mathieu-Daudé | 2020-10-17 | 3 | -17/+28 |
| * | target/mips/cp0_timer: Document TIMER_PERIOD origin | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -1/+11 |
| * | target/mips/cp0_timer: Explicit unit in variable name | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -9/+10 |
| * | target/mips: Move cpu_mips_get_random() with CP0 helpers | Philippe Mathieu-Daudé | 2020-10-17 | 3 | -26/+26 |
| * | target/mips/op_helper: Log unimplemented cache opcode | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -0/+9 |
| * | target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -0/+5 |
| * | target/mips/op_helper: Convert multiple if() to switch case | Philippe Mathieu-Daudé | 2020-10-17 | 1 | -4/+9 |
| * | target/mips: Add loongson-ext lsdc2 group of instructions | Jiaxun Yang | 2020-10-17 | 1 | -0/+179 |
| * | target/mips: Add loongson-ext lswc2 group of instructions (Part 2) | Jiaxun Yang | 2020-10-17 | 1 | -2/+180 |
| * | target/mips: Add loongson-ext lswc2 group of instructions (Part 1) | Jiaxun Yang | 2020-10-17 | 1 | -0/+86 |
| * | target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S> | Aleksandar Markovic | 2020-10-17 | 1 | -23/+81 |
| * | target/mips: Demacro helpers for M<ADD|SUB>F.<D|S> | Aleksandar Markovic | 2020-10-17 | 1 | -17/+46 |
| * | target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS> | Aleksandar Markovic | 2020-10-17 | 1 | -21/+40 |
| * | target/mips: Fix some comment spelling errors | zhaolichang | 2020-10-17 | 3 | -7/+7 |
* | | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ... | Peter Maydell | 2020-10-17 | 1 | -0/+1 |
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| * | | hax: unbreak accelerator cpu code after cpus.c split | Claudio Fontana | 2020-10-17 | 1 | -0/+1 |
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* | | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in... | Peter Maydell | 2020-10-16 | 4 | -28/+29 |
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| * | i386: Mark Icelake-Client CPU models deprecated | Robert Hoo | 2020-10-14 | 1 | -3/+7 |
| * | cpu: Introduce CPU model deprecation API | Robert Hoo | 2020-10-14 | 1 | -0/+8 |
| * | i386/kvm: Delete kvm_allows_irq0_override() | Eduardo Habkost | 2020-10-14 | 3 | -11/+0 |