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| * i386/kvm: Remove IRQ routing support checksEduardo Habkost2020-10-141-7/+0Star
| | | | | | | | | | | | | | | | | | | | KVM_CAP_IRQ_ROUTING is always available on x86, so replace checks for kvm_has_gsi_routing() and KVM_CAP_IRQ_ROUTING with asserts. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200922201922.2153598-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386/kvm: Require KVM_CAP_IRQ_ROUTINGEduardo Habkost2020-10-141-0/+5
| | | | | | | | | | | | | | | | | | | | KVM_CAP_IRQ_ROUTING is available since 2009 (Linux v2.6.30), so it's safe to just make it a requirement on x86. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200922201922.2153598-2-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * target/i386: Remove core_id assert check in CPUID 0x8000001EBabu Moger2020-10-141-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With x2apic enabled, configurations can have more that 255 cores. Noticed the device add test is hitting an assert when during cpu hotplug with core_id > 255. This is due to assert check in the CPUID 0x8000001E. Remove the assert check and fix the problem. Fixes the bug: Link: https://bugzilla.redhat.com/show_bug.cgi?id=1834200 Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <160072824160.9666.8890355282135970684.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386/kvm: fix FEATURE_HYPERV_EDX value in hyperv_passthrough caseZhenyu Wang2020-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | Fix typo to use correct edx value for FEATURE_HYPERV_EDX when hyperv_passthrough is enabled. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Message-Id: <20190820103030.12515-1-zhenyuw@linux.intel.com> Fixes: e48ddcc6ce13 ("i386/kvm: implement 'hv-passthrough' mode") Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: drop x86_cpu_get_supported_feature_word() forward declarationVitaly Kuznetsov2020-10-141-3/+0Star
| | | | | | | | | | | | | | | | | | We only use x86_cpu_get_supported_feature_word() after its implementation, no forward declaration needed. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200904145431.196885-3-vkuznets@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | i386: Register most CPU properties as class propertiesEduardo Habkost2020-10-131-32/+34
|/ | | | | | | | | | Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200921221045.699690-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target/sparc/int32_helper: Remove duplicated 'Tag Overflow' entryPhilippe Mathieu-Daudé2020-10-131-1/+0Star
| | | | | | | | | | Commit 0b09be2b2f ("Nicer debug output for exceptions") added twice the same "Tag Overflow" entry, remove the extra one. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20201011200112.3222822-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* target/i386/cpu: Update comment that mentions TexinfoMarkus Armbruster2020-10-121-1/+2
| | | | | | | | | | Missed in commit 41fba1618b "docs/system: convert the documentation of deprecated features to rST." Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200929075824.1517969-3-armbru@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* ppc: Fix return value in cpu_post_load() error pathGreg Kurz2020-10-091-4/+5
| | | | | | | | | | VMState handlers are supposed to return negative errno values on failure. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20200914123505.612812-4-groug@kaod.org> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: Add a return value to ppc_set_compat() and ppc_set_compat_all()Greg Kurz2020-10-092-13/+17
| | | | | | | | | | | | | | | | As recommended in "qapi/error.h", indicate success / failure with a return value. Since ppc_set_compat() is called from a VMState handler, let's make it an int so that it propagates any negative errno returned by kvmppc_set_compat(). Do the same for ppc_set_compat_all() for consistency, even if it isn't called in a context where a negative errno is required on failure. This will allow to simplify error handling in the callers. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20200914123505.612812-3-groug@kaod.org> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/arm: Make '-cpu max' have a 48-bit PAPeter Maydell2020-10-081-0/+4
| | | | | | | | | | | | QEMU supports a 48-bit physical address range, but we don't currently expose it in the '-cpu max' ID registers (you get the same range as Cortex-A57, which is 44 bits). Set the ID_AA64MMFR0.PARange field to indicate 48 bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
* hw/arm/virt: Implement kvm-steal-timeAndrew Jones2020-10-086-6/+131
| | | | | | | | | | | We add the kvm-steal-time CPU property and implement it for machvirt. A tiny bit of refactoring was also done to allow pmu and pvtime to use the same vcpu device helper functions. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-7-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm/kvm: Make uncalled stubs explicitly unreachableAndrew Jones2020-10-081-19/+32
| | | | | | | | | | | | | | | | | | | | When we compile without KVM support !defined(CONFIG_KVM) we generate stubs for functions that the linker will still encounter. Sometimes these stubs can be executed safely and are placed in paths where they get executed with or without KVM. Other functions should never be called without KVM. Those functions should be guarded by kvm_enabled(), but should also be robust to refactoring mistakes. Putting a g_assert_not_reached() in the function should help. Additionally, the g_assert_not_reached() calls may actually help the linker remove some code. We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't necessary at all - the only caller is in kvm.c Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-3-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hax: remove hax specific functions from global includesClaudio Fontana2020-10-057-6/+21
| | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* whpx: remove whpx specific functions from global includesClaudio Fontana2020-10-051-0/+17
| | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hvf: remove hvf specific functions from global includesClaudio Fontana2020-10-053-1/+10
| | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpus: add handle_interrupt to the CpusAccel interfaceClaudio Fontana2020-10-053-29/+0Star
| | | | | | | | | | | | | kvm: uses the generic handler qtest: uses the generic handler whpx: changed to use the generic handler (identical implementation) hax: changed to use the generic handler (identical implementation) hvf: changed to use the generic handler (identical implementation) tcg: adapt tcg-cpus to point to the tcg-specific handler Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpus: extract out hvf-specific code to target/i386/hvf/Claudio Fontana2020-10-054-0/+152
| | | | | | | | | | | register a "CpusAccel" interface for HVF as well. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> [added const] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpus: extract out whpx-specific code to target/i386/Claudio Fontana2020-10-054-1/+120
| | | | | | | | register a "CpusAccel" interface for WHPX as well. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpus: extract out hax-specific code to target/i386/Claudio Fontana2020-10-057-3/+148
| | | | | | | | register a "CpusAccel" interface for HAX as well. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* icount: rename functions to be consistent with the module nameClaudio Fontana2020-10-052-4/+4
| | | | | | | Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu-timers, icount: new modulesClaudio Fontana2020-10-053-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | refactoring of cpus.c continues with cpu timer state extraction. cpu-timers: responsible for the softmmu cpu timers state, including cpu clocks and ticks. icount: counts the TCG instructions executed. As such it is specific to the TCG accelerator. Therefore, it is built only under CONFIG_TCG. One complication is due to qtest, which uses an icount field to warp time as part of qtest (qtest_clock_warp). In order to solve this problem, provide a separate counter for qtest. This requires fixing assumptions scattered in the code that qtest_enabled() implies icount_enabled(), checking each specific case. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [remove redundant initialization with qemu_spice_init] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [fix lingering calls to icount_get] Signed-off-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell2020-10-052-11/+49
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * move target configuration to default-configs/targets (myself) * Memory failure event (Zhenwei) # gpg: Signature made Mon 05 Oct 2020 08:14:29 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: dockerfiles: add diffutils to Fedora tests: tcg: do not use implicit rules target-i386: post memory failure event to QMP qapi/run-state.json: introduce memory failure event target-i386: seperate MCIP & MCE_MASK error reason meson: move sparse detection to Meson and rewrite check_sparse.py default-configs: remove redundant keys default-configs: use TARGET_ARCH key configure: move OpenBSD W^X test to meson default-configs: remove default-configs/devices for user-mode targets configure: remove target configuration configure: remove useless config-target.mak symbols configure: compute derivatives of target name in meson configure: remove dead variable configure: move accelerator logic to meson configure: rewrite accelerator defaults as tests configure: convert accelerator variables to meson options default-configs: move files to default-configs/devices/ travis: remove TCI test Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # configure
| * target-i386: post memory failure event to QMPzhenwei pi2020-10-042-5/+32
| | | | | | | | | | | | | | | | | | | | | | Post memory failure event through QMP to handle hardware memory corrupted event. Rather than simply printing to the log, QEMU could report more effective message to the client. For example, if a guest receives an MCE, evacuating the host could be a good idea. Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <20200930100440.1060708-4-pizhenwei@bytedance.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: seperate MCIP & MCE_MASK error reasonzhenwei pi2020-10-041-7/+18
| | | | | | | | | | | | | | | | | | | | Previously we would only get a simple string "Triple fault" in qemu log. Add detailed message for the two reasons to describe why qemu has to reset the guest. Signed-off-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <20200930100440.1060708-2-pizhenwei@bytedance.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | disas: Enable capstone disassembly for s390xRichard Henderson2020-10-031-0/+4
|/ | | | | | | | | | Enable s390x, aka SYSZ, in the git submodule build. Set the capstone parameters for both s390x host and guest. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)David Hildenbrand2020-10-023-0/+9
| | | | | | | | | | As with the other crypto functions, we only implement subcode 0 (query) and no actual encryption/decryption. We now implement S390_FEAT_MSA_EXT_8. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: We support Miscellaneous-Instruction-Extensions Facility 2David Hildenbrand2020-10-021-0/+1
| | | | | | | | | We implement all relevant instructions. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)David Hildenbrand2020-10-025-0/+59
| | | | | | | | | | | | | We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)David Hildenbrand2020-10-022-0/+10
| | | | | | | | | | | | Just like BRANCH ON CONDITION - however the address is read from memory (always 8 bytes are read), we have to wrap the address manually. The address is read using current CPU DAT/address-space controls, just like ordinary data. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY HALFWORD (MGH)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | Just like MULTIPLY HALFWORD IMMEDIATE (MGHI), only the second operand (signed 16 bit) comes from memory. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY (MG, MGRK)David Hildenbrand2020-10-022-0/+15
| | | | | | | | | | Multiply two signed 64bit values and store the 128bit result in r1 (0-63) and r1 + 1 (64-127). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement SUBTRACT HALFWORD (SGH)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | Easy to wire up. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement ADD HALFWORD (AGH)David Hildenbrand2020-10-022-0/+2
| | | | | | | | | | Easy, just like ADD HALFWORD IMMEDIATE (AGHI). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/cpumodel: S390_FEAT_MISC_INSTRUCTION_EXT -> ↵David Hildenbrand2020-10-022-2/+2
| | | | | | | | | | | | | S390_FEAT_MISC_INSTRUCTION_EXT2 Let's avoid confusion with the "Miscellaneous-Instruction-Extensions Facility 1" Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Cc: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20200928122717.30586-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MONITOR CALLDavid Hildenbrand2020-10-024-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390: guest support for diagnose 0x318Collin Walling2020-10-027-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DIAGNOSE 0x318 (diag318) is an s390 instruction that allows the storage of diagnostic information that is collected by the firmware in the case of hardware/firmware service events. QEMU handles the instruction by storing the info in the CPU state. A subsequent register sync will communicate the data to the hypervisor. QEMU handles the migration via a VM State Description. This feature depends on the Extended-Length SCCB (els) feature. If els is not present, then a warning will be printed and the SCLP bit that allows the Linux kernel to execute the instruction will not be set. Availability of this instruction is determined by byte 134 (aka fac134) bit 0 of the SCLP Read Info block. This coincidentally expands into the space used for CPU entries, which means VMs running with the diag318 capability may not be able to read information regarding all CPUs unless the guest kernel supports an extended-length SCCB. This feature is not supported in protected virtualization mode. Signed-off-by: Collin Walling <walling@linux.ibm.com> Acked-by: Janosch Frank <frankja@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Message-Id: <20200915194416.107460-9-walling@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390/sclp: add extended-length sccb support for kvm guestCollin Walling2020-10-023-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As more features and facilities are added to the Read SCP Info (RSCPI) response, more space is required to store them. The space used to store these new features intrudes on the space originally used to store CPU entries. This means as more features and facilities are added to the RSCPI response, less space can be used to store CPU entries. With the Extended-Length SCCB (ELS) facility, a KVM guest can execute the RSCPI command and determine if the SCCB is large enough to store a complete reponse. If it is not large enough, then the required length will be set in the SCCB header. The caller of the SCLP command is responsible for creating a large-enough SCCB to store a complete response. Proper checking should be in place, and the caller should execute the command once-more with the large-enough SCCB. This facility also enables an extended SCCB for the Read CPU Info (RCPUI) command. When this facility is enabled, the boundary violation response cannot be a result from the RSCPI, RSCPI Forced, or RCPUI commands. In order to tolerate kernels that do not yet have full support for this feature, a "fixed" offset to the start of the CPU Entries within the Read SCP Info struct is set to allow for the original 248 max entries when this feature is disabled. Additionally, this is introduced as a CPU feature to protect the guest from migrating to a machine that does not support storing an extended SCCB. This could otherwise hinder the VM from being able to read all available CPU entries after migration (such as during re-ipl). Signed-off-by: Collin Walling <walling@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Message-Id: <20200915194416.107460-7-walling@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/arm: Fix SVE spliceRichard Henderson2020-10-011-1/+1
| | | | | | | | | | | | While converting to gen_gvec_ool_zzzp, we lost passing a->esz as the data argument to the function. Fixes: 36cbb7a8e71 Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Fix sve ldr/strRichard Henderson2020-10-011-2/+2
| | | | | | | | | | The mte update missed a bit when producing clean addresses. Fixes: b2aa8879b88 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Make isar_feature_aa32_fp16_arith() handle M-profilePeter Maydell2020-10-011-5/+26
| | | | | | | | | | | | | | The M-profile definition of the MVFR1 ID register differs slightly from the A-profile one, and in particular the check for "does the CPU support fp16 arithmetic" is not the same. We don't currently implement any M-profile CPUs with fp16 arithmetic, so this is not yet a visible bug, but correcting the logic now disarms this beartrap for when we eventually do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
* target/arm: Add ID register values for Cortex-M0Peter Maydell2020-10-011-0/+24
| | | | | | | | | | | Give the Cortex-M0 ID register values corresponding to its implemented behaviour. These will not be guest-visible but will be used to govern the behaviour of QEMU's emulation. We use the same values that the Cortex-M3 does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
* target/arm: Move id_pfr0, id_pfr1 into ARMISARegistersPeter Maydell2020-10-016-38/+42
| | | | | | | | | | | | | | | Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters sub-struct. We're going to want id_pfr1 for an isar_features check, and moving both at the same time avoids an odd inconsistency. Changes other than the ones to cpu.h and kvm64.c made automatically with: perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
* target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA checkPeter Maydell2020-10-013-4/+17
| | | | | | | | | | | | The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN bit in short-descriptor translation table format descriptors. This is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the feature bit with an ID register check, in line with our preference for ID register checks over feature bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
* target/i386: kvm: do not use kvm_check_extension to find paravirtual ↵Paolo Bonzini2020-09-301-32/+0Star
| | | | | | | | | | | capabilities Paravirtualized features have been listed in KVM_GET_SUPPORTED_CPUID since Linux 2.6.35 (commit 84478c829d0f, "KVM: x86: export paravirtual cpuid flags in KVM_GET_SUPPORTED_CPUID", 2010-05-19). It has been more than 10 years, so remove the fallback code. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: always create kvmclock deviceVitaly Kuznetsov2020-09-302-0/+6
| | | | | | | | | | | | | | | | | | | | QEMU's kvmclock device is only created when KVM PV feature bits for kvmclock (KVM_FEATURE_CLOCKSOURCE/KVM_FEATURE_CLOCKSOURCE2) are exposed to the guest. With 'kvm=off' cpu flag the device is not created and we don't call KVM_GET_CLOCK/KVM_SET_CLOCK upon migration. It was reported that without these call at least Hyper-V TSC page clocksouce (which can be enabled independently) gets broken after migration. Switch to creating kvmclock QEMU device unconditionally, it seems to always make sense to call KVM_GET_CLOCK/KVM_SET_CLOCK on migration. Use KVM_CAP_ADJUST_CLOCK check instead of CPUID feature bits. Reported-by: Antoine Damhet <antoine.damhet@blade-group.com> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200922151934.899555-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: Fix VM migration when interrupt based APF is enabledVitaly Kuznetsov2020-09-301-6/+6
| | | | | | | | | | | | | | | | | | | VM with interrupt based APF enabled fails to migrate: qemu-system-x86_64: error: failed to set MSR 0x4b564d02 to 0xf3 We have two issues: 1) There is a typo in kvm_put_msrs() and we write async_pf_int_msr to MSR_KVM_ASYNC_PF_EN (instead of MSR_KVM_ASYNC_PF_INT) 2) We restore MSR_KVM_ASYNC_PF_EN before MSR_KVM_ASYNC_PF_INT is set and this violates the check in KVM. Re-order MSR_KVM_ASYNC_PF_EN/MSR_KVM_ASYNC_PF_INT setting (and kvm_get_msrs() for consistency) and fix the typo. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200917102316.814804-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* helper_syscall x86_64: clear exception_is_intDouglas Crosher2020-09-301-0/+1
| | | | | | | | | | The exception_is_int flag may be set on entry to helper_syscall, e.g. after a prior interrupt that has returned, and processing EXCP_SYSCALL as an interrupt causes it to fail so clear this flag. Signed-off-by: Douglas Crosher <dtc-ubuntu@scieneer.com> Message-Id: <a7dab33e-eda6-f988-52e9-f3d32db7538d@scieneer.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not availableXiaoyao Li2020-09-301-0/+2
| | | | | | | | | | Per Intel SDM vol 1, 13.2, if CPUID.1:ECX.XSAVE[bit 26] is 0, the processor provides no further enumeration through CPUID function 0DH. QEMU does not do this for "-cpu host,-xsave". Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20200716082019.215316-2-xiaoyao.li@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: support KVM_FEATURE_ASYNC_PF_INTVitaly Kuznetsov2020-09-304-1/+32
| | | | | | | | | | | | | | | Linux-5.8 introduced interrupt based mechanism for 'page ready' events delivery and disabled the old, #PF based one (see commit 2635b5c4a0e4 "KVM: x86: interrupt based APF 'page ready' event delivery"). Linux guest switches to using in in 5.9 (see commit b1d405751cd5 "KVM: x86: Switch KVM guest to using interrupts for page ready APF delivery"). The feature has a new KVM_FEATURE_ASYNC_PF_INT bit assigned and the interrupt vector is set in MSR_KVM_ASYNC_PF_INT MSR. Support this in QEMU. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200908141206.357450-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-23 21:48:48 +0100