summaryrefslogtreecommitdiffstats
path: root/tcg/aarch64
Commit message (Expand)AuthorAgeFilesLines
* tcg/aarch64: Use LDP to load tlb mask+tableRichard Henderson2019-06-101-7/+8
* cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson2019-06-101-23/+6Star
* tcg: Create struct CPUTLBRichard Henderson2019-06-101-7/+3Star
* tcg/aarch64: Allow immediates for vector ORR and BICRichard Henderson2019-05-221-7/+83
* tcg/aarch64: Build vector immediates with two insnsRichard Henderson2019-05-221-0/+47
* tcg/aarch64: Use MVNI in tcg_out_dupi_vecRichard Henderson2019-05-221-0/+11
* tcg/aarch64: Split up is_fimmRichard Henderson2019-05-221-84/+119
* tcg/aarch64: Support vector bitwise select valueRichard Henderson2019-05-222-2/+24
* tcg: Add support for vector compare selectRichard Henderson2019-05-221-0/+1
* tcg: Add support for vector bitwise selectRichard Henderson2019-05-221-0/+1
* tcg/aarch64: Do not advertise minmax for MO_64Richard Henderson2019-05-141-4/+4
* tcg/aarch64: Support vector absolute valueRichard Henderson2019-05-142-1/+7
* tcg: Add support for vector absolute valueRichard Henderson2019-05-141-0/+1
* tcg/aarch64: Support vector variable shift opcodesRichard Henderson2019-05-143-1/+45
* tcg: Add INDEX_op_dupm_vecRichard Henderson2019-05-141-0/+4
* tcg/aarch64: Implement tcg_out_dupm_vecRichard Henderson2019-05-141-2/+35
* tcg: Add tcg_out_dupm_vec to the backend interfaceRichard Henderson2019-05-131-0/+6
* tcg: Manually expand INDEX_op_dup_vecRichard Henderson2019-05-131-5/+4Star
* tcg: Promote tcg_out_{dup,dupi}_vec to backend interfaceRichard Henderson2019-05-131-2/+10
* tcg: Return bool success from tcg_out_movRichard Henderson2019-05-131-2/+3
* tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson2019-04-241-6/+10
* tcg/aarch64: Support INDEX_op_extract2_{i32,i64}Richard Henderson2019-04-242-2/+13
* tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson2019-04-241-0/+2
* cputlb: Remove static tlb sizingRichard Henderson2019-01-281-1/+0Star
* tcg/aarch64: enable dynamic TLB sizingRichard Henderson2019-01-282-42/+60
* tcg: introduce dynamic TLB sizingEmilio G. Cota2019-01-281-0/+1
* tcg/aarch64: Implement vector minmax arithmeticRichard Henderson2019-01-282-1/+25
* tcg/aarch64: Implement vector saturating arithmeticRichard Henderson2019-01-282-1/+25
* tcg: Add opcodes for vector minmax arithmeticRichard Henderson2019-01-281-0/+1
* tcg: Add opcodes for vector saturated arithmeticRichard Henderson2019-01-281-0/+1
* tcg: Add TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson2018-12-171-0/+1
* tcg/aarch64: Return false on failure from patch_relocRichard Henderson2018-12-171-16/+21
* tcg: Return success from patch_relocRichard Henderson2018-12-171-1/+2
* tcg/aarch64: Fold away "noaddr" branch routinesRichard Henderson2018-12-171-19/+2Star
* tcg/aarch64: Remove reloc_pc26_atomicRichard Henderson2018-12-171-12/+0Star
* tcg/aarch64: limit mul_vec sizeAlex Bennée2018-07-191-1/+2
* tcg: Reduce max TB opcode countRichard Henderson2018-06-151-1/+1
* tcg/aarch64: Add vector operationsRichard Henderson2018-02-083-47/+569
* tcg/aarch64: Fully convert tcg_target_op_defRichard Henderson2017-09-171-131/+151
* tcg: Remove tcg_regset_set32Richard Henderson2017-09-171-16/+17
* tcg: Remove tcg_regset_clearRichard Henderson2017-09-171-1/+1
* tcg/aarch64: Use constant pool for moviRichard Henderson2017-09-072-30/+33
* tcg: Rearrange ldst label trackingRichard Henderson2017-09-072-1/+6
* tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.hRichard Henderson2017-09-072-9/+9
* tcg: Add tcg target default memory orderingPranith Kumar2017-09-051-0/+2
* tcg/aarch64: Enable indirect jump path using LDR (literal)Pranith Kumar2017-07-101-14/+28
* tcg/aarch64: Use ADRP+ADD to compute target addressPranith Kumar2017-07-101-6/+30
* tcg/aarch64: Introduce and use long branch to registerPranith Kumar2017-07-101-2/+13
* tcg/aarch64: Use ADR in tcg_out_moviRichard Henderson2017-06-191-1/+6
* tcg/aarch64: Implement goto_ptrRichard Henderson2017-06-052-3/+21
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 03:57:12 +0100