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* tcg/tci: Implement the disassembler properlyRichard Henderson2021-03-171-0/+283
| | | | | | | | | Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Hoist op_size checking into tci_args_*Richard Henderson2021-03-171-14/+73
| | | | | | | | | This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}Richard Henderson2021-03-171-66/+81
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bitsRichard Henderson2021-03-171-4/+4
| | | | | | | | | We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Clean up deposit operationsRichard Henderson2021-03-171-17/+16Star
| | | | | | | | | | | | Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrrRichard Henderson2021-03-171-5/+11
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrrrrRichard Henderson2021-03-171-11/+20
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reuse tci_args_l for goto_tbRichard Henderson2021-03-171-5/+3Star
| | | | | | | | | Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reuse tci_args_l for exit_tbRichard Henderson2021-03-171-9/+4Star
| | | | | | | | | | Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label != NULL has to be removed because that is a valid value for exit_tb. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reuse tci_args_l for calls.Richard Henderson2021-03-171-19/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_ri and tci_args_rIRichard Henderson2021-03-171-16/+22
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrcl and tci_args_rrrrclRichard Henderson2021-03-171-20/+32
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrrrcRichard Henderson2021-03-171-6/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_lRichard Henderson2021-03-171-2/+8
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrcRichard Henderson2021-03-171-10/+14
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrRichard Henderson2021-03-171-97/+57Star
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrRichard Henderson2021-03-171-36/+31Star
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrsRichard Henderson2021-03-171-44/+67
| | | | | | | | | | | | | Begin splitting out functions that do pure argument decode, without actually loading values from the register set. This means that decoding need not concern itself between input and output registers. We can assert that the register number is in range during decode, so that it is safe to simply dereference from regs[] later. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Rename tci_read_r to tci_read_rvalRichard Henderson2021-03-171-96/+96
| | | | | | | | | In the next patches, we want to use tci_read_r to return the raw register number. So rename the existing function, which returns the register value, to tci_read_rval. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64Richard Henderson2021-03-171-4/+0Star
| | | | | | | | | These operations are always available under different names: INDEX_op_ext_i32_i64 and INDEX_op_extu_i32_i64, so we remove no code with the ifdef. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge mov, not and neg operationsRichard Henderson2021-03-061-24/+5Star
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge bswap operationsRichard Henderson2021-03-061-18/+4Star
| | | | | | | This includes bswap16 and bswap32. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge extension operationsRichard Henderson2021-03-061-36/+8Star
| | | | | | | This includes ext8s, ext8u, ext16s, ext16u. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge basic arithmetic operationsRichard Henderson2021-03-061-54/+21Star
| | | | | | | This includes add, sub, mul, and, or, xor. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reduce use of tci_read_r64Richard Henderson2021-03-061-51/+42Star
| | | | | | | | | In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_read_r32sRichard Henderson2021-03-061-18/+2Star
| | | | | | | Use explicit casts for ext32s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_read_r32Richard Henderson2021-03-061-68/+54Star
| | | | | | | | Use explicit casts for ext32u opcodes, and allow truncation to happen for other users. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_read_r16sRichard Henderson2021-03-061-22/+4Star
| | | | | | | Use explicit casts for ext16s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_read_r16Richard Henderson2021-03-061-21/+7Star
| | | | | | | | | Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st16 opcodes, and with the call for bswap16 opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_read_r8sRichard Henderson2021-03-061-21/+4Star
| | | | | | | Use explicit casts for ext8s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_read_r8Richard Henderson2021-03-061-18/+5Star
| | | | | | | | Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Use exec/cpu_ldst.h interfacesRichard Henderson2021-03-061-45/+28Star
| | | | | | | | | | | Use the provided cpu_ldst.h interfaces. This fixes the build vs the unconverted uses of g2h(), adds missed memory trace events, and correctly recognizes when a SIGSEGV belongs to the guest via set_helper_retaddr(). Fixes: 3e8f1628e864 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove TCG_CONSTRichard Henderson2021-02-051-122/+67Star
| | | | | | | | | | Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson2021-02-051-4/+4
| | | | | | | | | | | | | | This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove TODO as unusedRichard Henderson2021-02-051-8/+0Star
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Implement 64-bit divisionRichard Henderson2021-02-051-3/+19
| | | | | | | | | Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*Richard Henderson2021-02-051-12/+0Star
| | | | | | | | | We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Use g_assert_not_reachedRichard Henderson2021-02-051-8/+7Star
| | | | | | | | | | Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_{st_i32,st32_i64}Richard Henderson2021-02-051-6/+1Star
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Move stack bounds check to compile-timeRichard Henderson2021-02-051-2/+0Star
| | | | | | | | | | | | | The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_st16_{i32,i64}Richard Henderson2021-02-051-7/+1Star
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_st8_{i32,i64}Richard Henderson2021-02-051-7/+1Star
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}Richard Henderson2021-02-051-6/+1Star
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_ld16s_{i32,i64}Richard Henderson2021-02-051-4/+1Star
| | | | | | | | Eliminating a TODO for ld16s_i64. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_ld16u_{i32,i64}Richard Henderson2021-02-051-8/+5Star
| | | | | | | | Eliminating a TODO for ld16u_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_ld8s_{i32,i64}Richard Henderson2021-02-051-8/+5Star
| | | | | | | | Eliminating a TODO for ld8s_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Merge INDEX_op_ld8u_{i32,i64}Richard Henderson2021-02-051-7/+13
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Inline tci_write_reg64 into 64-bit callersRichard Henderson2021-02-051-33/+27Star
| | | | | | | | | | | Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Inline tci_write_reg32 into all callersRichard Henderson2021-02-051-36/+30Star
| | | | | | | | | | For a 64-bit TCI, the upper bits of a 32-bit operation are undefined (much like a native ppc64 32-bit operation). It simplifies everything if we don't force-extend the result. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Inline tci_write_reg16 into the only callerRichard Henderson2021-02-051-9/+1Star
| | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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