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* avoid TABs in files that only contain a fewPaolo Bonzini2019-01-111-2/+2
* qemu/queue.h: simplify reverse access to QTAILQPaolo Bonzini2019-01-112-4/+4
* qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini2019-01-111-1/+1
* tcg: Improve call argument loadingRichard Henderson2018-12-251-1/+2
* tcg: Record register preferences during livenessRichard Henderson2018-12-251-32/+165
* tcg: Add TCG_OPF_BB_EXITRichard Henderson2018-12-253-10/+16
* tcg: Split out more subroutines from liveness_pass_1Richard Henderson2018-12-251-12/+23
* tcg: Rename and adjust liveness_pass_1 helpersRichard Henderson2018-12-251-8/+5Star
* tcg: Reindent parts of liveness_pass_1Richard Henderson2018-12-251-67/+70
* tcg: Dump register preference info with livenessRichard Henderson2018-12-252-10/+37
* tcg: Improve register allocation for matching constraintsRichard Henderson2018-12-251-12/+24
* tcg: Add output_pref to TCGOpRichard Henderson2018-12-252-7/+14
* tcg: Add preferred_reg argument to tcg_reg_alloc_do_moviRichard Henderson2018-12-251-4/+5
* tcg: Add preferred_reg argument to temp_syncRichard Henderson2018-12-251-8/+8
* tcg: Add preferred_reg argument to temp_loadRichard Henderson2018-12-251-9/+9
* tcg: Add preferred_reg argument to tcg_reg_allocRichard Henderson2018-12-251-22/+81
* tcg: Add reachable_code_passRichard Henderson2018-12-251-0/+76
* tcg: Reference count labelsRichard Henderson2018-12-254-1/+25
* tcg: Add TCG_CALL_NO_RETURNRichard Henderson2018-12-251-0/+2
* tcg: Renumber TCG_CALL_* flagsRichard Henderson2018-12-251-3/+3
* tcg/riscv: Add the target init codeAlistair Francis2018-12-251-0/+31
* tcg/riscv: Add the prologue generation and register the JITAlistair Francis2018-12-251-0/+111
* tcg/riscv: Add the out op decoderAlistair Francis2018-12-251-0/+496
* tcg/riscv: Add direct load and store instructionsAlistair Francis2018-12-251-0/+158
* tcg/riscv: Add slowpath load and store instructionsAlistair Francis2018-12-251-0/+256
* tcg/riscv: Add branch and jump instructionsAlistair Francis2018-12-251-0/+145
* tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis2018-12-251-0/+55
* tcg/riscv: Add the out load and store instructionsAlistair Francis2018-12-251-0/+65
* tcg/riscv: Add the extract instructionsAlistair Francis2018-12-251-0/+34
* tcg/riscv: Add the mov and movi instructionAlistair Francis2018-12-251-0/+86
* tcg/riscv: Add the relocation functionsAlistair Francis2018-12-251-0/+88
* tcg/riscv: Add the instruction emittersAlistair Francis2018-12-251-0/+48
* tcg/riscv: Add the immediate encodersAlistair Francis2018-12-251-0/+90
* tcg/riscv: Add support for the constraintsAlistair Francis2018-12-251-0/+168
* tcg/riscv: Add the tcg target registersAlistair Francis2018-12-251-0/+118
* tcg/riscv: Add the tcg-target.h fileAlistair Francis2018-12-251-0/+177
* tcg: Drop nargs from tcg_op_insert_{before,after}Emilio G. Cota2018-12-173-10/+8Star
* tcg/mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITSAlistair Francis2018-12-171-1/+1
* tcg: Add TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson2018-12-179-2/+126
* tcg/optimize: Optimize bswapRichard Henderson2018-12-171-0/+12
* tcg: Clean up generic bswap64Richard Henderson2018-12-171-27/+20Star
* tcg: Clean up generic bswap32Richard Henderson2018-12-171-27/+27
* tcg/i386: Add setup_guest_base_seg for FreeBSDRichard Henderson2018-12-171-0/+9
* tcg/i386: Precompute all guest_base parametersRichard Henderson2018-12-171-61/+40Star
* tcg/i386: Assume 32-bit values are zero-extendedRichard Henderson2018-12-171-63/+40Star
* tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guestsRichard Henderson2018-12-172-2/+9
* tcg/i386: Propagate is64 to tcg_out_qemu_ld_slow_pathRichard Henderson2018-12-171-5/+8
* tcg/i386: Propagate is64 to tcg_out_qemu_ld_directRichard Henderson2018-12-171-6/+7
* tcg/s390x: Return false on failure from patch_relocRichard Henderson2018-12-171-11/+23
* tcg/ppc: Return false on failure from patch_relocRichard Henderson2018-12-171-11/+21