1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
|
/*
* ARMv7M NVIC object
*
* Copyright (c) 2017 Linaro Ltd
* Written by Peter Maydell <peter.maydell@linaro.org>
*
* This code is licensed under the GPL version 2 or later.
*/
#ifndef HW_ARM_ARMV7M_NVIC_H
#define HW_ARM_ARMV7M_NVIC_H
#include "target/arm/cpu.h"
#include "hw/sysbus.h"
#include "hw/timer/armv7m_systick.h"
#include "qom/object.h"
#define TYPE_NVIC "armv7m_nvic"
typedef struct NVICState NVICState;
DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
TYPE_NVIC)
/* Highest permitted number of exceptions (architectural limit) */
#define NVIC_MAX_VECTORS 512
/* Number of internal exceptions */
#define NVIC_INTERNAL_VECTORS 16
typedef struct VecInfo {
/* Exception priorities can range from -3 to 255; only the unmodifiable
* priority values for RESET, NMI and HardFault can be negative.
*/
int16_t prio;
uint8_t enabled;
uint8_t pending;
uint8_t active;
uint8_t level; /* exceptions <=15 never set level */
} VecInfo;
struct NVICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
ARMCPU *cpu;
VecInfo vectors[NVIC_MAX_VECTORS];
/* If the v8M security extension is implemented, some of the internal
* exceptions are banked between security states (ie there exists both
* a Secure and a NonSecure version of the exception and its state):
* HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)
* The rest (including all the external exceptions) are not banked, though
* they may be configurable to target either Secure or NonSecure state.
* We store the secure exception state in sec_vectors[] for the banked
* exceptions, and otherwise use only vectors[] (including for exceptions
* like SecureFault that unconditionally target Secure state).
* Entries in sec_vectors[] for non-banked exception numbers are unused.
*/
VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];
/* The PRIGROUP field in AIRCR is banked */
uint32_t prigroup[M_REG_NUM_BANKS];
uint8_t num_prio_bits;
/* v8M NVIC_ITNS state (stored as a bool per bit) */
bool itns[NVIC_MAX_VECTORS];
/* The following fields are all cached state that can be recalculated
* from the vectors[] and sec_vectors[] arrays and the prigroup field:
* - vectpending
* - vectpending_is_secure
* - exception_prio
* - vectpending_prio
*/
unsigned int vectpending; /* highest prio pending enabled exception */
/* true if vectpending is a banked secure exception, ie it is in
* sec_vectors[] rather than vectors[]
*/
bool vectpending_is_s_banked;
int exception_prio; /* group prio of the highest prio active exception */
int vectpending_prio; /* group prio of the exeception in vectpending */
MemoryRegion sysregmem;
MemoryRegion sysreg_ns_mem;
MemoryRegion systickmem;
MemoryRegion systick_ns_mem;
MemoryRegion ras_mem;
MemoryRegion container;
MemoryRegion defaultmem;
uint32_t num_irq;
qemu_irq excpout;
qemu_irq sysresetreq;
SysTickState systick[M_REG_NUM_BANKS];
};
#endif
|
