blob: eeaf49bbac3162cf40b7b65d229b83f313654869 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/*
* IMX SPI Controller
*
* Copyright 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef IMX_SPI_H
#define IMX_SPI_H
#include "hw/sysbus.h"
#include "hw/ssi/ssi.h"
#include "qemu/bitops.h"
#include "qemu/fifo32.h"
#include "qom/object.h"
#define ECSPI_FIFO_SIZE 64
#define ECSPI_RXDATA 0
#define ECSPI_TXDATA 1
#define ECSPI_CONREG 2
#define ECSPI_CONFIGREG 3
#define ECSPI_INTREG 4
#define ECSPI_DMAREG 5
#define ECSPI_STATREG 6
#define ECSPI_PERIODREG 7
#define ECSPI_TESTREG 8
#define ECSPI_MSGDATA 16
#define ECSPI_MAX 17
/* ECSPI_CONREG */
#define ECSPI_CONREG_EN (1 << 0)
#define ECSPI_CONREG_HT (1 << 1)
#define ECSPI_CONREG_XCH (1 << 2)
#define ECSPI_CONREG_SMC (1 << 3)
#define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4
#define ECSPI_CONREG_CHANNEL_MODE_LENGTH 4
#define ECSPI_CONREG_DRCTL_SHIFT 16
#define ECSPI_CONREG_DRCTL_LENGTH 2
#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18
#define ECSPI_CONREG_CHANNEL_SELECT_LENGTH 2
#define ECSPI_CONREG_BURST_LENGTH_SHIFT 20
#define ECSPI_CONREG_BURST_LENGTH_LENGTH 12
/* ECSPI_CONFIGREG */
#define ECSPI_CONFIGREG_SS_CTL_SHIFT 8
#define ECSPI_CONFIGREG_SS_CTL_LENGTH 4
/* ECSPI_INTREG */
#define ECSPI_INTREG_TEEN (1 << 0)
#define ECSPI_INTREG_TDREN (1 << 1)
#define ECSPI_INTREG_TFEN (1 << 2)
#define ECSPI_INTREG_RREN (1 << 3)
#define ECSPI_INTREG_RDREN (1 << 4)
#define ECSPI_INTREG_RFEN (1 << 5)
#define ECSPI_INTREG_ROEN (1 << 6)
#define ECSPI_INTREG_TCEN (1 << 7)
/* ECSPI_DMAREG */
#define ECSPI_DMAREG_RXTDEN (1 << 31)
#define ECSPI_DMAREG_RXDEN (1 << 23)
#define ECSPI_DMAREG_TEDEN (1 << 7)
#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16
#define ECSPI_DMAREG_RX_THRESHOLD_LENGTH 6
/* ECSPI_STATREG */
#define ECSPI_STATREG_TE (1 << 0)
#define ECSPI_STATREG_TDR (1 << 1)
#define ECSPI_STATREG_TF (1 << 2)
#define ECSPI_STATREG_RR (1 << 3)
#define ECSPI_STATREG_RDR (1 << 4)
#define ECSPI_STATREG_RF (1 << 5)
#define ECSPI_STATREG_RO (1 << 6)
#define ECSPI_STATREG_TC (1 << 7)
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
/* number of chip selects supported */
#define ECSPI_NUM_CS 4
#define TYPE_IMX_SPI "imx.spi"
OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
struct IMXSPIState {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion iomem;
qemu_irq irq;
qemu_irq cs_lines[ECSPI_NUM_CS];
SSIBus *bus;
uint32_t regs[ECSPI_MAX];
Fifo32 rx_fifo;
Fifo32 tx_fifo;
int16_t burst_length;
};
#endif /* IMX_SPI_H */
|
