blob: afc86a153fc04a4113a7324118d3f78b29bb6917 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
#ifndef XTENSA_TARGET_SYSCALL_H
#define XTENSA_TARGET_SYSCALL_H
#define UNAME_MACHINE "xtensa"
#define UNAME_MINIMUM_RELEASE "3.19"
#define TARGET_CLONE_BACKWARDS
#define MMAP_SHIFT TARGET_PAGE_BITS
typedef uint32_t xtensa_reg_t;
typedef struct {
} xtregs_opt_t; /* TODO */
struct target_pt_regs {
xtensa_reg_t pc; /* 4 */
xtensa_reg_t ps; /* 8 */
xtensa_reg_t depc; /* 12 */
xtensa_reg_t exccause; /* 16 */
xtensa_reg_t excvaddr; /* 20 */
xtensa_reg_t debugcause; /* 24 */
xtensa_reg_t wmask; /* 28 */
xtensa_reg_t lbeg; /* 32 */
xtensa_reg_t lend; /* 36 */
xtensa_reg_t lcount; /* 40 */
xtensa_reg_t sar; /* 44 */
xtensa_reg_t windowbase; /* 48 */
xtensa_reg_t windowstart; /* 52 */
xtensa_reg_t syscall; /* 56 */
xtensa_reg_t icountlevel; /* 60 */
xtensa_reg_t scompare1; /* 64 */
xtensa_reg_t threadptr; /* 68 */
/* Additional configurable registers that are used by the compiler. */
xtregs_opt_t xtregs_opt;
/* Make sure the areg field is 16 bytes aligned. */
int align[0] __attribute__ ((aligned(16)));
/* current register frame.
* Note: The ESF for kernel exceptions ends after 16 registers!
*/
xtensa_reg_t areg[16];
};
#define TARGET_MCL_CURRENT 1
#define TARGET_MCL_FUTURE 2
#define TARGET_MCL_ONFAULT 4
#endif
|
