1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
|
#include "macros.inc"
test_suite load_store
.macro load_ok_test op, type, data, value
.data
.align 4
1:
\type \data
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b
addi a4, a4, 1
mov a5, a4
\op a5, a3, 0
movi a6, \value
assert eq, a5, a6
.endm
#if XCHAL_UNALIGNED_LOAD_EXCEPTION
.macro load_unaligned_test will_trap, op, type, data, value
.data
.align 4
.byte 0
1:
\type \data
.previous
reset_ps
.ifeq \will_trap
set_vector kernel, 0
.else
set_vector kernel, 2f
.endif
movi a3, 1b
addi a4, a4, 1
mov a5, a4
1:
\op a5, a3, 0
.ifeq \will_trap
movi a6, \value
assert eq, a5, a6
.else
test_fail
2:
rsr a6, exccause
movi a7, 9
assert eq, a6, a7
rsr a6, epc1
movi a7, 1b
assert eq, a6, a7
rsr a6, excvaddr
assert eq, a6, a3
assert eq, a5, a4
.endif
reset_ps
.endm
#else
.macro load_unaligned_test will_trap, op, type, data, value
.data
.align 4
1:
\type \data
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b + 1
addi a4, a4, 1
mov a5, a4
\op a5, a3, 0
movi a6, \value
assert eq, a5, a6
.endm
#endif
.macro store_ok_test op, type, value
.data
.align 4
.byte 0, 0, 0, 0x55
1:
\type 0
2:
.byte 0xaa
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b
movi a5, \value
\op a5, a3, 0
movi a3, 2b
l8ui a5, a3, 0
movi a6, 0xaa
assert eq, a5, a6
movi a3, 1b - 1
l8ui a5, a3, 0
movi a6, 0x55
assert eq, a5, a6
.endm
#if XCHAL_UNALIGNED_STORE_EXCEPTION
.macro store_unaligned_test will_trap, op, nop, type, value
.data
.align 4
.byte 0x55
1:
\type 0
2:
.byte 0xaa
.previous
reset_ps
.ifeq \will_trap
set_vector kernel, 0
.else
set_vector kernel, 4f
.endif
movi a3, 1b
movi a5, \value
3:
\op a5, a3, 0
.ifne \will_trap
test_fail
4:
rsr a6, exccause
movi a7, 9
assert eq, a6, a7
rsr a6, epc1
movi a7, 3b
assert eq, a6, a7
rsr a6, excvaddr
assert eq, a6, a3
l8ui a5, a3, 0
assert eqi, a5, 0
.endif
reset_ps
movi a3, 2b
l8ui a5, a3, 0
movi a6, 0xaa
assert eq, a5, a6
movi a3, 1b - 1
l8ui a5, a3, 0
movi a6, 0x55
assert eq, a5, a6
.endm
#else
.macro store_unaligned_test will_trap, sop, lop, type, value
.data
.align 4
.byte 0x55
1:
\type 0
.previous
reset_ps
set_vector kernel, 0
movi a3, 1b
movi a5, \value
\sop a5, a3, 0
movi a3, 1b - 1
\lop a6, a3, 0
assert eq, a5, a6
.endm
#endif
test load_ok
load_ok_test l16si, .short, 0x00001234, 0x00001234
load_ok_test l16si, .short, 0x000089ab, 0xffff89ab
load_ok_test l16ui, .short, 0x00001234, 0x00001234
load_ok_test l16ui, .short, 0x000089ab, 0x000089ab
load_ok_test l32i, .word, 0x12345678, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
load_ok_test l32ai, .word, 0x12345678, 0x12345678
#endif
test_end
#undef WILL_TRAP
#if XCHAL_UNALIGNED_LOAD_HW
#define WILL_TRAP 0
#else
#define WILL_TRAP 1
#endif
test load_unaligned
load_unaligned_test WILL_TRAP, l16si, .short, 0x00001234, 0x00001234
load_unaligned_test WILL_TRAP, l16si, .short, 0x000089ab, 0xffff89ab
load_unaligned_test WILL_TRAP, l16ui, .short, 0x00001234, 0x00001234
load_unaligned_test WILL_TRAP, l16ui, .short, 0x000089ab, 0x000089ab
load_unaligned_test WILL_TRAP, l32i, .word, 0x12345678, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
load_unaligned_test 1, l32ai, .word, 0x12345678, 0x12345678
#endif
test_end
test store_ok
store_ok_test s16i, .short, 0x00001234
store_ok_test s32i, .word, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
store_ok_test s32ri, .word, 0x12345678
#endif
test_end
#undef WILL_TRAP
#if XCHAL_UNALIGNED_STORE_HW
#define WILL_TRAP 0
#else
#define WILL_TRAP 1
#endif
test store_unaligned
store_unaligned_test WILL_TRAP, s16i, l16ui, .short, 0x00001234
store_unaligned_test WILL_TRAP, s32i, l32i, .word, 0x12345678
#if XCHAL_HAVE_RELEASE_SYNC
store_unaligned_test 1, s32ri, l32i, .word, 0x12345678
#endif
test_end
test_suite_end
|
