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| author | Michael Brown | 2016-07-03 13:52:20 +0200 |
|---|---|---|
| committer | Michael Brown | 2016-07-03 13:52:20 +0200 |
| commit | 3bb61c33c2d77ac9a1a512d809576f3444b6b1ed (patch) | |
| tree | e3de22abca94db6d351f793cc0c5e085ba161762 /src/arch/i386/include/pcbios | |
| parent | [bios] Do not enable interrupts when printing to the console (diff) | |
| download | ipxe-3bb61c33c2d77ac9a1a512d809576f3444b6b1ed.tar.gz ipxe-3bb61c33c2d77ac9a1a512d809576f3444b6b1ed.tar.xz ipxe-3bb61c33c2d77ac9a1a512d809576f3444b6b1ed.zip | |
[pxe] Disable interrupts on the PIC before starting NBP
Some BIOSes (observed with an HP Gen9) seem to spuriously enable
interrupts at the PIC. This causes problems with NBPs such as GRUB
which use the UNDI API (thereby enabling interrupts on the NIC)
without first hooking an interrupt service routine. In this
situation, the interrupt will end up being handled by the default BIOS
ISR, which will typically just send an EOI and return. Since nothing
in this handler causes the NIC to deassert the interrupt, this will
result in an interrupt storm.
Entertainingly, some BIOSes are immune to this problem because the
default ISR sends the EOI only to the slave PIC; this effectively
disables the interrupt.
Work around this problem by disabling the interrupt on the PIC before
invoking the PXE NBP. An NBP that expects to make use of interrupts
will need to be configuring the PIC anyway, so it is probably safe to
assume that it will explicitly reenable the interrupt.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/arch/i386/include/pcbios')
0 files changed, 0 insertions, 0 deletions