diff options
| author | Michael Brown | 2016-05-11 22:44:23 +0200 |
|---|---|---|
| committer | Michael Brown | 2016-05-12 12:16:41 +0200 |
| commit | 601706688bbb5502538627feb92752760d0d9f24 (patch) | |
| tree | c5d2c0b3038f1ddc70a1a5306dcfcf4de93cbaad /src/arch | |
| parent | [efi] Guard against GetStatus() failing to return a NULL TX buffer (diff) | |
| download | ipxe-601706688bbb5502538627feb92752760d0d9f24.tar.gz ipxe-601706688bbb5502538627feb92752760d0d9f24.tar.xz ipxe-601706688bbb5502538627feb92752760d0d9f24.zip | |
[arm] Use CNTVCT_EL0 as profiling timestamp
The raw cycle counter at PMCCNTR_EL0 works in qemu but seems to always
read as zero on physical hardware (tested on Juno r1 and Cavium
ThunderX), even after ensuring that PMCR_EL0.E and PMCNTENSET_EL0.C
are both enabled.
Use CNTVCT_EL0 instead; this seems to count at a lower resolution
(tens of CPU cycles), but is usable for profiling.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm64/include/bits/profile.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/arch/arm64/include/bits/profile.h b/src/arch/arm64/include/bits/profile.h index cad02ea4..62ffa377 100644 --- a/src/arch/arm64/include/bits/profile.h +++ b/src/arch/arm64/include/bits/profile.h @@ -21,9 +21,7 @@ profile_timestamp ( void ) { uint64_t cycles; /* Read cycle counter */ - __asm__ __volatile__ ( "msr PMCR_EL0, %1\n\t" - "mrs %0, PMCCNTR_EL0\n\t" - : "=r" ( cycles ) : "r" ( 1 ) ); + __asm__ __volatile__ ( "mrs %0, CNTVCT_EL0\n\t" : "=r" ( cycles ) ); return cycles; } |