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authorMichael Brown2012-07-10 11:52:56 +0200
committerMichael Brown2012-07-10 12:21:22 +0200
commit9f0b2d25a8e889899711b81213e91d042c58002f (patch)
treee4e97becaeccf60bd34b14896a590f0ef4330469 /src/drivers/net/intel.c
parent[intel] Refill receive ring only after enabling receiver (diff)
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[intel] Explicitly enable descriptor queues
On i350 the datasheet contradicts itself in stating that the default value of RXDCTL.ENABLE for queue zero is both set (according to the "Receive Initialization" section) and unset (according to the "Receive Descriptor Control - RXDCTL" section). Empirical evidence suggests that the default value is unset. Explicitly enable both transmit and receive queues to avoid any ambiguity. Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/intel.c')
-rw-r--r--src/drivers/net/intel.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/drivers/net/intel.c b/src/drivers/net/intel.c
index 8153e095..1fdce1cb 100644
--- a/src/drivers/net/intel.c
+++ b/src/drivers/net/intel.c
@@ -363,6 +363,7 @@ static void intel_check_link ( struct net_device *netdev ) {
static int intel_create_ring ( struct intel_nic *intel,
struct intel_ring *ring ) {
physaddr_t address;
+ uint32_t dctl;
/* Allocate descriptor ring. Align ring on its own size to
* prevent any possible page-crossing errors due to hardware
@@ -393,6 +394,11 @@ static int intel_create_ring ( struct intel_nic *intel,
writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
+ /* Enable ring */
+ dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
+ dctl |= INTEL_xDCTL_ENABLE;
+ writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
+
DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
intel, ring->reg, ( ( unsigned long long ) address ),
( ( unsigned long long ) address + ring->len ) );