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| author | Michael Brown | 2013-04-03 16:20:55 +0200 |
|---|---|---|
| committer | Michael Brown | 2013-04-19 00:56:05 +0200 |
| commit | c2ba57e517031c751b93ffc59fa30ffa4d03ba0d (patch) | |
| tree | 876cc77a2db70b9710f8c7986b62c31ca1388909 /src/drivers/net/intel.h | |
| parent | [bios] Fix screen clearing on buggy BIOSes (diff) | |
| download | ipxe-c2ba57e517031c751b93ffc59fa30ffa4d03ba0d.tar.gz ipxe-c2ba57e517031c751b93ffc59fa30ffa4d03ba0d.tar.xz ipxe-c2ba57e517031c751b93ffc59fa30ffa4d03ba0d.zip | |
[intel] Remove hardcoded offsets for descriptor ring registers
The Intel 10 Gigabit NICs use the same simplified (aka "legacy")
descriptor format and the same layout for descriptor register blocks
as the Intel 1 Gigabit NICs. The offsets of the descriptor register
blocks are not the same.
Simplify reuse of the existing code by removing all hardcoded offsets
for registers within descriptor register blocks, and ensuring that all
offsets are calculated using the descriptor register block base
address provided via intel_init_ring().
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/intel.h')
| -rw-r--r-- | src/drivers/net/intel.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/drivers/net/intel.h b/src/drivers/net/intel.h index e9e9052b..18a86ea3 100644 --- a/src/drivers/net/intel.h +++ b/src/drivers/net/intel.h @@ -175,18 +175,6 @@ enum intel_descriptor_status { #define INTEL_xDCTL 0x28 #define INTEL_xDCTL_ENABLE 0x02000000UL /**< Queue enable */ -/** Receive Descriptor Head */ -#define INTEL_RDH ( INTEL_RD + INTEL_xDH ) - -/** Receive Descriptor Tail */ -#define INTEL_RDT ( INTEL_RD + INTEL_xDT ) - -/** Transmit Descriptor Head */ -#define INTEL_TDH ( INTEL_TD + INTEL_xDH ) - -/** Transmit Descriptor Tail */ -#define INTEL_TDT ( INTEL_TD + INTEL_xDT ) - /** Receive Address Low */ #define INTEL_RAL0 0x05400UL |