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| author | Michael Brown | 2013-05-01 10:15:51 +0200 |
|---|---|---|
| committer | Michael Brown | 2013-05-01 10:21:56 +0200 |
| commit | 9b1ec3132fed94c644c77a5e59a8ba2112110455 (patch) | |
| tree | 434cb2d4a7417c6f5483521855ae706e0d7e0bda /src/drivers/net/realtek.c | |
| parent | [romprefix] Report failure cause when unable to open payload (diff) | |
| download | ipxe-9b1ec3132fed94c644c77a5e59a8ba2112110455.tar.gz ipxe-9b1ec3132fed94c644c77a5e59a8ba2112110455.tar.xz ipxe-9b1ec3132fed94c644c77a5e59a8ba2112110455.zip | |
[realtek] Ensure EEPROM writes reach chip before starting udelay()
On some systems, it appears to be possible for writes to the EEPROM
registers to be delayed for long enough that the EEPROM's setup and
hold times are violated, resulting in invalid data being read from the
EEPROM.
Fix by inserting a PCI read cycle immediately after writes to
RTL_9346CR, to ensure that the write has completed before starting the
udelay() used to time the SPI bus transitions.
Reported-by: Gelip <mrgelip@gmail.com>
Tested-by: Gelip <mrgelip@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/realtek.c')
| -rw-r--r-- | src/drivers/net/realtek.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c index 70c0ac1c..f7b5ec58 100644 --- a/src/drivers/net/realtek.c +++ b/src/drivers/net/realtek.c @@ -74,6 +74,7 @@ static void realtek_spi_open_bit ( struct bit_basher *basher ) { /* Enable EEPROM access */ writeb ( RTL_9346CR_EEM_EEPROM, rtl->regs + RTL_9346CR ); + readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */ } /** @@ -87,6 +88,7 @@ static void realtek_spi_close_bit ( struct bit_basher *basher ) { /* Disable EEPROM access */ writeb ( RTL_9346CR_EEM_NORMAL, rtl->regs + RTL_9346CR ); + readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */ } /** @@ -129,6 +131,7 @@ static void realtek_spi_write_bit ( struct bit_basher *basher, reg &= ~mask; reg |= ( data & mask ); writeb ( reg, rtl->regs + RTL_9346CR ); + readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */ DBG_ENABLE ( DBGLVL_IO ); } |