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| author | Michael Brown | 2014-03-04 17:30:06 +0100 |
|---|---|---|
| committer | Michael Brown | 2014-03-04 17:30:06 +0100 |
| commit | ac5c2e851b14b153860c98eb01a5add982c91380 (patch) | |
| tree | 7cf248d3eb006d546bcb38a6d3d4f1ba1f3f7de6 /src/drivers/net/realtek.h | |
| parent | [bzimage] Report exact initrd length via bzImage header (diff) | |
| download | ipxe-ac5c2e851b14b153860c98eb01a5add982c91380.tar.gz ipxe-ac5c2e851b14b153860c98eb01a5add982c91380.tar.xz ipxe-ac5c2e851b14b153860c98eb01a5add982c91380.zip | |
[realtek] Include link status register details in debug messages
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/realtek.h')
| -rw-r--r-- | src/drivers/net/realtek.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/drivers/net/realtek.h b/src/drivers/net/realtek.h index a17f963f..e426dc5a 100644 --- a/src/drivers/net/realtek.h +++ b/src/drivers/net/realtek.h @@ -187,7 +187,13 @@ enum realtek_legacy_status { /** Media Status Register (byte, 8139 only) */ #define RTL_MSR 0x58 +#define RTL_MSR_TXFCE 0x80 /**< TX flow control enabled */ +#define RTL_MSR_RXFCE 0x40 /**< RX flow control enabled */ +#define RTL_MSR_AUX_STATUS 0x10 /**< Aux power present */ +#define RTL_MSR_SPEED_10 0x08 /**< 10Mbps */ #define RTL_MSR_LINKB 0x04 /**< Inverse of link status */ +#define RTL_MSR_TXPF 0x02 /**< TX pause flag */ +#define RTL_MSR_RXPF 0x01 /**< RX pause flag */ /** PHY Access Register (dword, 8169 only) */ #define RTL_PHYAR 0x60 @@ -204,7 +210,14 @@ enum realtek_legacy_status { /** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */ #define RTL_PHYSTATUS 0x6c +#define RTL_PHYSTATUS_ENTBI 0x80 /**< TBI / GMII mode */ +#define RTL_PHYSTATUS_TXFLOW 0x40 /**< TX flow control enabled */ +#define RTL_PHYSTATUS_RXFLOW 0x20 /**< RX flow control enabled */ +#define RTL_PHYSTATUS_1000MF 0x10 /**< 1000Mbps full-duplex */ +#define RTL_PHYSTATUS_100M 0x08 /**< 100Mbps */ +#define RTL_PHYSTATUS_10M 0x04 /**< 10Mbps */ #define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */ +#define RTL_PHYSTATUS_FULLDUP 0x01 /**< Full duplex */ /** Transmit Priority Polling Register (byte, 8139C+ only) */ #define RTL_TPPOLL_8139CP 0xd9 |