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| author | Michael Brown | 2017-07-10 13:38:39 +0200 |
|---|---|---|
| committer | Michael Brown | 2017-07-10 13:41:23 +0200 |
| commit | 74f934a14e8d0bead8086433596745e7c2b67990 (patch) | |
| tree | 2ca329bea266f5aa5507ca1a80c5a90ee5d7a6a4 /src/drivers/net/smsc75xx.h | |
| parent | [smscusb] Move non-inline register access functions to smscusb.c (diff) | |
| download | ipxe-74f934a14e8d0bead8086433596745e7c2b67990.tar.gz ipxe-74f934a14e8d0bead8086433596745e7c2b67990.tar.xz ipxe-74f934a14e8d0bead8086433596745e7c2b67990.zip | |
[smscusb] Allow for alternative PHY register layouts
The LAN78xx PHY interrupt source and mask registers do not match those
used by the SMSC75xx and SMSC95xx.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/smsc75xx.h')
| -rw-r--r-- | src/drivers/net/smsc75xx.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/drivers/net/smsc75xx.h b/src/drivers/net/smsc75xx.h index 0a330fd9..f8bcefb7 100644 --- a/src/drivers/net/smsc75xx.h +++ b/src/drivers/net/smsc75xx.h @@ -66,6 +66,18 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); /** MII register base */ #define SMSC75XX_MII_BASE 0x120 +/** PHY interrupt source MII register */ +#define SMSC75XX_MII_PHY_INTR_SOURCE 29 + +/** PHY interrupt mask MII register */ +#define SMSC75XX_MII_PHY_INTR_MASK 30 + +/** PHY interrupt: auto-negotiation complete */ +#define SMSC75XX_PHY_INTR_ANEG_DONE 0x0040 + +/** PHY interrupt: link down */ +#define SMSC75XX_PHY_INTR_LINK_DOWN 0x0010 + /** MAC address perfect filter register base */ #define SMSC75XX_ADDR_FILT_BASE 0x300 |