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author | Michael Brown | 2017-04-14 11:09:57 +0200 |
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committer | Michael Brown | 2017-04-14 11:09:57 +0200 |
commit | e6616da8b8647fe928b633e39c9e2e656aed5249 (patch) | |
tree | 8d72be5eb29c2cb38ba5c597f013ee461e070295 /src/drivers/net | |
parent | [block] Allow use of a non-default EFI SAN boot filename (diff) | |
download | ipxe-e6616da8b8647fe928b633e39c9e2e656aed5249.tar.gz ipxe-e6616da8b8647fe928b633e39c9e2e656aed5249.tar.xz ipxe-e6616da8b8647fe928b633e39c9e2e656aed5249.zip |
[intel] Show original CTRL and STATUS values in debugging output
In situations where iPXE fails to reach link-up as expected, it is
useful to know the original values of the CTRL and STATUS registers
prior to our reset attempt.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net')
-rw-r--r-- | src/drivers/net/intel.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/drivers/net/intel.c b/src/drivers/net/intel.c index 534252ba..548bf90a 100644 --- a/src/drivers/net/intel.c +++ b/src/drivers/net/intel.c @@ -268,6 +268,12 @@ static int intel_reset ( struct intel_nic *intel ) { uint32_t pba; uint32_t ctrl; uint32_t status; + uint32_t orig_ctrl; + uint32_t orig_status; + + /* Record initial control and status register values */ + orig_ctrl = ctrl = readl ( intel->regs + INTEL_CTRL ); + orig_status = readl ( intel->regs + INTEL_STATUS ); /* Force RX and TX packet buffer allocation, to work around an * errata in ICH devices. @@ -285,7 +291,6 @@ static int intel_reset ( struct intel_nic *intel ) { } /* Always reset MAC. Required to reset the TX and RX rings. */ - ctrl = readl ( intel->regs + INTEL_CTRL ); writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL ); mdelay ( INTEL_RESET_DELAY_MS ); @@ -309,9 +314,10 @@ static int intel_reset ( struct intel_nic *intel ) { status = readl ( intel->regs + INTEL_STATUS ); if ( ( intel->flags & INTEL_NO_PHY_RST ) || ( status & INTEL_STATUS_LU ) ) { - DBGC ( intel, "INTEL %p %sMAC reset (ctrl %08x)\n", intel, + DBGC ( intel, "INTEL %p %sMAC reset (%08x/%08x was " + "%08x/%08x)\n", intel, ( ( intel->flags & INTEL_NO_PHY_RST ) ? "forced " : "" ), - ctrl ); + ctrl, status, orig_ctrl, orig_status ); return 0; } @@ -323,8 +329,10 @@ static int intel_reset ( struct intel_nic *intel ) { /* PHY reset is not self-clearing on all models */ writel ( ctrl, intel->regs + INTEL_CTRL ); mdelay ( INTEL_RESET_DELAY_MS ); + status = readl ( intel->regs + INTEL_STATUS ); - DBGC ( intel, "INTEL %p MAC+PHY reset (ctrl %08x)\n", intel, ctrl ); + DBGC ( intel, "INTEL %p MAC+PHY reset (%08x/%08x was %08x/%08x)\n", + intel, ctrl, status, orig_ctrl, orig_status ); return 0; } |