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authorSimon Rettberg2024-04-12 14:00:15 +0200
committerSimon Rettberg2024-04-12 14:00:15 +0200
commit98dc341428e247141f120d05fac48c4e144a4c0f (patch)
tree3ebacb37927e338383ac64c2e20eb0b2f820cb85 /src/drivers
parentMerge branch 'master' into openslx (diff)
parentMerge branch 'ipxe:master' into aqc1xx (diff)
downloadipxe-98dc341428e247141f120d05fac48c4e144a4c0f.tar.gz
ipxe-98dc341428e247141f120d05fac48c4e144a4c0f.tar.xz
ipxe-98dc341428e247141f120d05fac48c4e144a4c0f.zip
Merge branch 'aqc1xx' into openslx
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/bus/ecam.c27
-rw-r--r--src/drivers/infiniband/arbel.c6
-rw-r--r--src/drivers/infiniband/hermon.c13
-rw-r--r--src/drivers/infiniband/linda.c4
-rw-r--r--src/drivers/infiniband/qib7322.c4
-rw-r--r--src/drivers/net/3c595.c4
-rw-r--r--src/drivers/net/3c90x.c12
-rw-r--r--src/drivers/net/ath/ath5k/ath5k.c8
-rw-r--r--src/drivers/net/b44.c2
-rw-r--r--src/drivers/net/bnxt/bnxt.c399
-rw-r--r--src/drivers/net/bnxt/bnxt.h215
-rw-r--r--src/drivers/net/bnxt/bnxt_dbg.h6
-rw-r--r--src/drivers/net/bnxt/bnxt_hsi.h229
-rw-r--r--src/drivers/net/davicom.c2
-rw-r--r--src/drivers/net/dmfe.c2
-rw-r--r--src/drivers/net/eepro100.c10
-rw-r--r--src/drivers/net/forcedeth.c22
-rw-r--r--src/drivers/net/intel.c1
-rw-r--r--src/drivers/net/iphone.c2
-rw-r--r--src/drivers/net/marvell/aqc1xx.c643
-rw-r--r--src/drivers/net/marvell/aqc1xx.h270
-rw-r--r--src/drivers/net/marvell/atl2_hw.c235
-rw-r--r--src/drivers/net/marvell/atl2_hw.h94
-rw-r--r--src/drivers/net/marvell/atl_hw.c321
-rw-r--r--src/drivers/net/marvell/atl_hw.h83
-rw-r--r--src/drivers/net/ns8390.c12
-rw-r--r--src/drivers/net/pcnet32.c2
-rw-r--r--src/drivers/net/prism2_plx.c4
-rw-r--r--src/drivers/net/rhine.c4
-rw-r--r--src/drivers/net/rtl818x/rtl8180.c2
-rw-r--r--src/drivers/net/sky2.c2
-rw-r--r--src/drivers/net/sundance.c2
-rw-r--r--src/drivers/net/tg3/tg3.c108
-rw-r--r--src/drivers/net/tlan.c14
-rw-r--r--src/drivers/net/tulip.c28
35 files changed, 2542 insertions, 250 deletions
diff --git a/src/drivers/bus/ecam.c b/src/drivers/bus/ecam.c
index 1d57bd2a..5e3debdd 100644
--- a/src/drivers/bus/ecam.c
+++ b/src/drivers/bus/ecam.c
@@ -127,7 +127,7 @@ static int ecam_access ( struct pci_device *pci ) {
/* Reuse mapping if possible */
if ( ( pci->busdevfn - ecam.range.start ) < ecam.range.count )
- return 0;
+ return ecam.rc;
/* Clear any existing mapping */
if ( ecam.regs ) {
@@ -145,12 +145,22 @@ static int ecam_access ( struct pci_device *pci ) {
if ( ecam.range.start > pci->busdevfn ) {
DBGC ( &ecam, "ECAM found no allocation for " PCI_FMT "\n",
PCI_ARGS ( pci ) );
+ rc = -ENOENT;
goto err_find;
}
/* Map configuration space for this allocation */
base = le64_to_cpu ( ecam.alloc.base );
+ base += ( ecam.alloc.start * ECAM_SIZE * PCI_BUSDEVFN ( 0, 1, 0, 0 ) );
len = ( ecam.range.count * ECAM_SIZE );
+ if ( base != ( ( unsigned long ) base ) ) {
+ DBGC ( &ecam, "ECAM %04x:[%02x-%02x] could not map "
+ "[%08llx,%08llx) outside CPU range\n",
+ le16_to_cpu ( ecam.alloc.segment ), ecam.alloc.start,
+ ecam.alloc.end, base, ( base + len ) );
+ rc = -ERANGE;
+ goto err_range;
+ }
ecam.regs = ioremap ( base, len );
if ( ! ecam.regs ) {
DBGC ( &ecam, "ECAM %04x:[%02x-%02x] could not map "
@@ -164,12 +174,14 @@ static int ecam_access ( struct pci_device *pci ) {
DBGC ( &ecam, "ECAM %04x:[%02x-%02x] mapped [%08llx,%08llx) -> %p\n",
le16_to_cpu ( ecam.alloc.segment ), ecam.alloc.start,
ecam.alloc.end, base, ( base + len ), ecam.regs );
+ ecam.rc = 0;
return 0;
iounmap ( ecam.regs );
err_ioremap:
+ err_range:
err_find:
- ecam.range.count = 0;
+ ecam.rc = rc;
return rc;
}
@@ -235,7 +247,7 @@ int ecam_write ( struct pci_device *pci, unsigned int location,
if ( ( rc = ecam_access ( pci ) ) != 0 )
return rc;
- /* Read from address */
+ /* Write to address */
index = ( pci->busdevfn - ecam.range.start );
addr = ( ecam.regs + ( index * ECAM_SIZE ) + where );
switch ( len ) {
@@ -252,6 +264,15 @@ int ecam_write ( struct pci_device *pci, unsigned int location,
assert ( 0 );
}
+ /* Read from address, to guarantee completion of the write
+ *
+ * PCIe configuration space registers may not have read side
+ * effects. Reading back is therefore always safe to do, and
+ * guarantees that the write has reached the device.
+ */
+ mb();
+ ecam_read ( pci, location, &value );
+
return 0;
}
diff --git a/src/drivers/infiniband/arbel.c b/src/drivers/infiniband/arbel.c
index 293c1b64..8be06d93 100644
--- a/src/drivers/infiniband/arbel.c
+++ b/src/drivers/infiniband/arbel.c
@@ -545,8 +545,8 @@ static int arbel_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
union arbelprm_mad mad_ifc;
int rc;
- linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
- mad_size_mismatch );
+ /* Sanity check */
+ static_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ) );
/* Copy in request packet */
memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
@@ -3139,8 +3139,8 @@ static void arbel_remove ( struct pci_device *pci ) {
}
static struct pci_device_id arbel_nics[] = {
- PCI_ROM ( 0x15b3, 0x6282, "mt25218", "MT25218 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x6274, "mt25204", "MT25204 HCA driver", 0 ),
+ PCI_ROM ( 0x15b3, 0x6282, "mt25218", "MT25218 HCA driver", 0 ),
};
struct pci_driver arbel_driver __pci_driver = {
diff --git a/src/drivers/infiniband/hermon.c b/src/drivers/infiniband/hermon.c
index c09baf7a..e5c3544f 100644
--- a/src/drivers/infiniband/hermon.c
+++ b/src/drivers/infiniband/hermon.c
@@ -779,8 +779,8 @@ static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
union hermonprm_mad mad_ifc;
int rc;
- linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
- mad_size_mismatch );
+ /* Sanity check */
+ static_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ) );
/* Copy in request packet */
memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
@@ -4214,6 +4214,9 @@ static void hermon_bofm_remove ( struct pci_device *pci ) {
}
static struct pci_device_id hermon_nics[] = {
+ /* Mellanox ConnectX-3 VPI (ethernet + infiniband) */
+ PCI_ROM ( 0x15b3, 0x1003, "mt4099", "ConnectX-3 HCA driver", 0 ),
+ PCI_ROM ( 0x15b3, 0x1007, "mt4103", "ConnectX-3 Pro HCA driver", 0 ),
/* Mellanox ConnectX VPI (ethernet + infiniband) */
PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver", 0 ),
@@ -4226,17 +4229,13 @@ static struct pci_device_id hermon_nics[] = {
PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x673c, "mt26428", "MT26428 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x6746, "mt26438", "MT26438 HCA driver", 0 ),
- PCI_ROM ( 0x15b3, 0x6778, "mt26488", "MT26488 HCA driver", 0 ),
/* Mellanox ConnectX-2 EN (ethernet only) */
PCI_ROM ( 0x15b3, 0x6750, "mt26448", "MT26448 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x675a, "mt26458", "MT26458 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x6764, "mt26468", "MT26468 HCA driver", 0 ),
PCI_ROM ( 0x15b3, 0x676e, "mt26478", "MT26478 HCA driver", 0 ),
-
- /* Mellanox ConnectX-3 VPI (ethernet + infiniband) */
- PCI_ROM ( 0x15b3, 0x1003, "mt4099", "ConnectX-3 HCA driver", 0 ),
- PCI_ROM ( 0x15b3, 0x1007, "mt4103", "ConnectX-3 Pro HCA driver", 0 ),
+ PCI_ROM ( 0x15b3, 0x6778, "mt26488", "MT26488 HCA driver", 0 ),
};
struct pci_driver hermon_driver __pci_driver = {
diff --git a/src/drivers/infiniband/linda.c b/src/drivers/infiniband/linda.c
index 8c591266..0c8a043a 100644
--- a/src/drivers/infiniband/linda.c
+++ b/src/drivers/infiniband/linda.c
@@ -721,7 +721,7 @@ static int linda_init_recv ( struct linda *linda ) {
eager_array_size_other = LINDA_EAGER_ARRAY_SIZE_17CTX_OTHER;
break;
default:
- linker_assert ( 0, invalid_LINDA_NUM_CONTEXTS );
+ build_assert ( 0 );
return -EINVAL;
}
@@ -1108,7 +1108,7 @@ static int linda_post_recv ( struct ib_device *ibdev,
case 16384: bufsize = LINDA_EAGER_BUFFER_16K; break;
case 32768: bufsize = LINDA_EAGER_BUFFER_32K; break;
case 65536: bufsize = LINDA_EAGER_BUFFER_64K; break;
- default: linker_assert ( 0, invalid_rx_payload_size );
+ default: build_assert ( 0 );
bufsize = LINDA_EAGER_BUFFER_NONE;
}
diff --git a/src/drivers/infiniband/qib7322.c b/src/drivers/infiniband/qib7322.c
index da055b74..a011dafc 100644
--- a/src/drivers/infiniband/qib7322.c
+++ b/src/drivers/infiniband/qib7322.c
@@ -893,7 +893,7 @@ static int qib7322_init_recv ( struct qib7322 *qib7322 ) {
eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_18CTX_USER;
break;
default:
- linker_assert ( 0, invalid_QIB7322_NUM_CONTEXTS );
+ build_assert ( 0 );
return -EINVAL;
}
@@ -1351,7 +1351,7 @@ static int qib7322_post_recv ( struct ib_device *ibdev,
case 16384: bufsize = QIB7322_EAGER_BUFFER_16K; break;
case 32768: bufsize = QIB7322_EAGER_BUFFER_32K; break;
case 65536: bufsize = QIB7322_EAGER_BUFFER_64K; break;
- default: linker_assert ( 0, invalid_rx_payload_size );
+ default: build_assert ( 0 );
bufsize = QIB7322_EAGER_BUFFER_NONE;
}
diff --git a/src/drivers/net/3c595.c b/src/drivers/net/3c595.c
index 92d38cfc..c6983100 100644
--- a/src/drivers/net/3c595.c
+++ b/src/drivers/net/3c595.c
@@ -523,10 +523,12 @@ static struct nic_operations t595_operations = {
};
static struct pci_device_id t595_nics[] = {
+PCI_ROM(0x10b7, 0x4500, "3c450-1", "3Com450 HomePNA Tornado", 0),
PCI_ROM(0x10b7, 0x5900, "3c590", "3Com590", 0), /* Vortex 10Mbps */
PCI_ROM(0x10b7, 0x5950, "3c595", "3Com595", 0), /* Vortex 100baseTx */
PCI_ROM(0x10b7, 0x5951, "3c595-1", "3Com595", 0), /* Vortex 100baseT4 */
PCI_ROM(0x10b7, 0x5952, "3c595-2", "3Com595", 0), /* Vortex 100base-MII */
+PCI_ROM(0x10b7, 0x7646, "3csoho100-tx-1", "3CSOHO100-TX", 0), /* Hurricane */
PCI_ROM(0x10b7, 0x9000, "3c900-tpo", "3Com900-TPO", 0), /* 10 Base TPO */
PCI_ROM(0x10b7, 0x9001, "3c900-t4", "3Com900-Combo", 0), /* 10/100 T4 */
PCI_ROM(0x10b7, 0x9004, "3c900b-tpo", "3Com900B-TPO", 0), /* 10 Base TPO */
@@ -535,8 +537,6 @@ PCI_ROM(0x10b7, 0x9006, "3c900b-tpb2", "3Com900B-2/T", 0), /* 10 Base TP and
PCI_ROM(0x10b7, 0x900a, "3c900b-fl", "3Com900B-FL", 0), /* 10 Base F */
PCI_ROM(0x10b7, 0x9800, "3c980-cyclone-1", "3Com980-Cyclone", 0), /* Cyclone */
PCI_ROM(0x10b7, 0x9805, "3c9805-1", "3Com9805", 0), /* Dual Port Server Cyclone */
-PCI_ROM(0x10b7, 0x7646, "3csoho100-tx-1", "3CSOHO100-TX", 0), /* Hurricane */
-PCI_ROM(0x10b7, 0x4500, "3c450-1", "3Com450 HomePNA Tornado", 0),
};
PCI_DRIVER ( t595_driver, t595_nics, PCI_NO_CLASS );
diff --git a/src/drivers/net/3c90x.c b/src/drivers/net/3c90x.c
index 1b8190c4..a94473ef 100644
--- a/src/drivers/net/3c90x.c
+++ b/src/drivers/net/3c90x.c
@@ -955,16 +955,20 @@ static int a3c90x_probe(struct pci_device *pci)
static struct pci_device_id a3c90x_nics[] = {
/* Original 90x revisions: */
+ PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A", 0),
+ PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B", 0),
+ PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado", 0),
PCI_ROM(0x10b7, 0x6055, "3c556", "3C556", 0), /* Huricane */
+ PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX", 0), /* Hurricane */
PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO", 0), /* 10 Base TPO */
PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo", 0), /* 10/100 T4 */
- PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX", 0), /* 100 Base TX / 10/100 TPO */
- PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4", 0), /* 100 Base T4 / 10 Base Combo */
/* Newer 90xB revisions: */
PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO", 0), /* 10 Base TPO */
PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo", 0), /* 10 Base Combo */
PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T", 0), /* 10 Base TP and Base2 */
PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL", 0), /* 10 Base FL */
+ PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX", 0), /* 100 Base TX / 10/100 TPO */
+ PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4", 0), /* 100 Base T4 / 10 Base Combo */
PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX", 0), /* 10/100 TPO */
PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4", 0), /* 10/100 T4 */
PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058", 0), /* Cyclone 10/100/BNC */
@@ -975,10 +979,6 @@ static struct pci_device_id a3c90x_nics[] = {
PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm", "3Com20B-EMB WNM", 0),
PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone", 0), /* Cyclone */
PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805", 0), /* Dual Port Server Cyclone */
- PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX", 0), /* Hurricane */
- PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado", 0),
- PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A", 0),
- PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B", 0),
};
struct pci_driver a3c90x_driver __pci_driver = {
diff --git a/src/drivers/net/ath/ath5k/ath5k.c b/src/drivers/net/ath/ath5k/ath5k.c
index e43eb0aa..643884d4 100644
--- a/src/drivers/net/ath/ath5k/ath5k.c
+++ b/src/drivers/net/ath/ath5k/ath5k.c
@@ -65,14 +65,11 @@ FILE_LICENCE ( BSD3 );
/* Known PCI ids */
static struct pci_device_id ath5k_nics[] = {
- PCI_ROM(0x168c, 0x0207, "ath5210e", "Atheros 5210 early", AR5K_AR5210),
+ PCI_ROM(0x10b7, 0x0013, "rdag675", "3com 3CRDAG675", AR5K_AR5212),
PCI_ROM(0x168c, 0x0007, "ath5210", "Atheros 5210", AR5K_AR5210),
PCI_ROM(0x168c, 0x0011, "ath5311", "Atheros 5311 (AHB)", AR5K_AR5211),
PCI_ROM(0x168c, 0x0012, "ath5211", "Atheros 5211", AR5K_AR5211),
PCI_ROM(0x168c, 0x0013, "ath5212", "Atheros 5212", AR5K_AR5212),
- PCI_ROM(0xa727, 0x0013, "ath5212c","3com Ath 5212", AR5K_AR5212),
- PCI_ROM(0x10b7, 0x0013, "rdag675", "3com 3CRDAG675", AR5K_AR5212),
- PCI_ROM(0x168c, 0x1014, "ath5212m", "Ath 5212 miniPCI", AR5K_AR5212),
PCI_ROM(0x168c, 0x0014, "ath5212x14", "Atheros 5212 x14", AR5K_AR5212),
PCI_ROM(0x168c, 0x0015, "ath5212x15", "Atheros 5212 x15", AR5K_AR5212),
PCI_ROM(0x168c, 0x0016, "ath5212x16", "Atheros 5212 x16", AR5K_AR5212),
@@ -83,6 +80,9 @@ static struct pci_device_id ath5k_nics[] = {
PCI_ROM(0x168c, 0x001b, "ath5413", "Atheros 5413 Eagle", AR5K_AR5212),
PCI_ROM(0x168c, 0x001c, "ath5212e", "Atheros 5212 PCI-E", AR5K_AR5212),
PCI_ROM(0x168c, 0x001d, "ath2417", "Atheros 2417 Nala", AR5K_AR5212),
+ PCI_ROM(0x168c, 0x0207, "ath5210e", "Atheros 5210 early", AR5K_AR5210),
+ PCI_ROM(0x168c, 0x1014, "ath5212m", "Ath 5212 miniPCI", AR5K_AR5212),
+ PCI_ROM(0xa727, 0x0013, "ath5212c","3com Ath 5212", AR5K_AR5212),
};
#define ATH5K_SPMBL_NO 1
diff --git a/src/drivers/net/b44.c b/src/drivers/net/b44.c
index 1ca7e2e5..30ece557 100644
--- a/src/drivers/net/b44.c
+++ b/src/drivers/net/b44.c
@@ -945,8 +945,8 @@ static struct net_device_operations b44_operations = {
static struct pci_device_id b44_nics[] = {
- PCI_ROM(0x14e4, 0x4401, "BCM4401", "BCM4401", 0),
PCI_ROM(0x14e4, 0x170c, "BCM4401-B0", "BCM4401-B0", 0),
+ PCI_ROM(0x14e4, 0x4401, "BCM4401", "BCM4401", 0),
PCI_ROM(0x14e4, 0x4402, "BCM4401-B1", "BCM4401-B1", 0),
};
diff --git a/src/drivers/net/bnxt/bnxt.c b/src/drivers/net/bnxt/bnxt.c
index 605aea32..a127f6ce 100644
--- a/src/drivers/net/bnxt/bnxt.c
+++ b/src/drivers/net/bnxt/bnxt.c
@@ -24,6 +24,11 @@ static int bnxt_rx_complete ( struct net_device *dev, struct rx_pkt_cmpl *rx );
void bnxt_link_evt ( struct bnxt *bp, struct hwrm_async_event_cmpl *evt );
static struct pci_device_id bnxt_nics[] = {
+ PCI_ROM( 0x14e4, 0x1604, "14e4-1604", "14e4-1604", 0 ),
+ PCI_ROM( 0x14e4, 0x1605, "14e4-1605", "14e4-1605", 0 ),
+ PCI_ROM( 0x14e4, 0x1606, "14e4-1606", "14e4-1606", 0 ),
+ PCI_ROM( 0x14e4, 0x1609, "14e4-1609", "14e4-1609", 0 ),
+ PCI_ROM( 0x14e4, 0x1614, "14e4-1614", "14e4-1614", 0 ),
PCI_ROM( 0x14e4, 0x16c0, "14e4-16C0", "14e4-16C0", 0 ),
PCI_ROM( 0x14e4, 0x16c1, "14e4-16C1", "14e4-16C1", BNXT_FLAG_PCI_VF ),
PCI_ROM( 0x14e4, 0x16c8, "14e4-16C8", "14e4-16C8", 0 ),
@@ -62,26 +67,22 @@ static struct pci_device_id bnxt_nics[] = {
PCI_ROM( 0x14e4, 0x16ef, "14e4-16EF", "14e4-16EF", 0 ),
PCI_ROM( 0x14e4, 0x16f0, "14e4-16F0", "14e4-16F0", 0 ),
PCI_ROM( 0x14e4, 0x16f1, "14e4-16F1", "14e4-16F1", 0 ),
- PCI_ROM( 0x14e4, 0x1604, "14e4-1604", "14e4-1604", 0 ),
- PCI_ROM( 0x14e4, 0x1605, "14e4-1605", "14e4-1605", 0 ),
- PCI_ROM( 0x14e4, 0x1606, "14e4-1606", "14e4-1606", 0 ),
- PCI_ROM( 0x14e4, 0x1609, "14e4-1609", "14e4-1609", 0 ),
- PCI_ROM( 0x14e4, 0x1614, "14e4-1614", "14e4-1614", 0 ),
- PCI_ROM( 0x14e4, 0xd802, "14e4-D802", "14e4-D802", 0 ),
- PCI_ROM( 0x14e4, 0xd804, "14e4-D804", "14e4-D804", 0 ),
PCI_ROM( 0x14e4, 0x1750, "14e4-1750", "14e4-1750", 0 ),
- PCI_ROM( 0x14e4, 0x1802, "14e4-1802", "14e4-1802", 0 ),
- PCI_ROM( 0x14e4, 0x1805, "14e4-1805", "14e4-1805", 0 ),
PCI_ROM( 0x14e4, 0x1751, "14e4-1751", "14e4-1751", 0 ),
- PCI_ROM( 0x14e4, 0x1801, "14e4-1801", "14e4-1801", 0 ),
- PCI_ROM( 0x14e4, 0x1804, "14e4-1804", "14e4-1804", 0 ),
PCI_ROM( 0x14e4, 0x1752, "14e4-1752", "14e4-1752", 0 ),
+ PCI_ROM( 0x14e4, 0x1760, "14e4-1760", "14e4-1760", 0 ),
PCI_ROM( 0x14e4, 0x1800, "14e4-1800", "14e4-1800", 0 ),
+ PCI_ROM( 0x14e4, 0x1801, "14e4-1801", "14e4-1801", 0 ),
+ PCI_ROM( 0x14e4, 0x1802, "14e4-1802", "14e4-1802", 0 ),
PCI_ROM( 0x14e4, 0x1803, "14e4-1803", "14e4-1803", 0 ),
+ PCI_ROM( 0x14e4, 0x1804, "14e4-1804", "14e4-1804", 0 ),
+ PCI_ROM( 0x14e4, 0x1805, "14e4-1805", "14e4-1805", 0 ),
PCI_ROM( 0x14e4, 0x1806, "14e4-1806", "14e4-1806", BNXT_FLAG_PCI_VF ),
PCI_ROM( 0x14e4, 0x1807, "14e4-1807", "14e4-1807", BNXT_FLAG_PCI_VF ),
PCI_ROM( 0x14e4, 0x1808, "14e4-1808", "14e4-1808", BNXT_FLAG_PCI_VF ),
PCI_ROM( 0x14e4, 0x1809, "14e4-1809", "14e4-1809", BNXT_FLAG_PCI_VF ),
+ PCI_ROM( 0x14e4, 0xd802, "14e4-D802", "14e4-D802", 0 ),
+ PCI_ROM( 0x14e4, 0xd804, "14e4-D804", "14e4-D804", 0 ),
};
/**
@@ -181,7 +182,7 @@ static void bnxt_set_link ( struct bnxt *bp )
netdev_link_down ( bp->dev );
}
-static void thor_db ( struct bnxt *bp, u32 idx, u32 xid, u32 flag )
+static void dev_p5_db ( struct bnxt *bp, u32 idx, u32 xid, u32 flag )
{
void *off;
u64 val;
@@ -196,10 +197,28 @@ static void thor_db ( struct bnxt *bp, u32 idx, u32 xid, u32 flag )
write64 ( val, off );
}
+static void dev_p7_db ( struct bnxt *bp, u32 idx, u32 xid, u32 flag, u32 epoch, u32 toggle )
+{
+ void *off;
+ u64 val;
+
+ off = ( void * ) ( bp->bar1 );
+
+ val = ( ( u64 )DBC_MSG_XID ( xid, flag ) << 32 ) |
+ ( u64 )DBC_MSG_IDX ( idx ) |
+ ( u64 )DBC_MSG_EPCH ( epoch ) |
+ ( u64 )DBC_MSG_TOGGLE ( toggle );
+ write64 ( val, off );
+}
+
static void bnxt_db_nq ( struct bnxt *bp )
{
- if ( bp->thor )
- thor_db ( bp, ( u32 )bp->nq.cons_id,
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
+ dev_p7_db ( bp, ( u32 )bp->nq.cons_id,
+ ( u32 )bp->nq_ring_id, DBC_DBC_TYPE_NQ_ARM,
+ ( u32 )bp->nq.epoch, 0 );
+ else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
+ dev_p5_db ( bp, ( u32 )bp->nq.cons_id,
( u32 )bp->nq_ring_id, DBC_DBC_TYPE_NQ_ARM );
else
write32 ( CMPL_DOORBELL_KEY_CMPL, ( bp->bar1 + 0 ) );
@@ -207,8 +226,12 @@ static void bnxt_db_nq ( struct bnxt *bp )
static void bnxt_db_cq ( struct bnxt *bp )
{
- if ( bp->thor )
- thor_db ( bp, ( u32 )bp->cq.cons_id,
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
+ dev_p7_db ( bp, ( u32 )bp->cq.cons_id,
+ ( u32 )bp->cq_ring_id, DBC_DBC_TYPE_CQ_ARMALL,
+ ( u32 )bp->cq.epoch, ( u32 )bp->nq.toggle );
+ else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
+ dev_p5_db ( bp, ( u32 )bp->cq.cons_id,
( u32 )bp->cq_ring_id, DBC_DBC_TYPE_CQ_ARMALL );
else
write32 ( CQ_DOORBELL_KEY_IDX ( bp->cq.cons_id ),
@@ -217,16 +240,22 @@ static void bnxt_db_cq ( struct bnxt *bp )
static void bnxt_db_rx ( struct bnxt *bp, u32 idx )
{
- if ( bp->thor )
- thor_db ( bp, idx, ( u32 )bp->rx_ring_id, DBC_DBC_TYPE_SRQ );
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
+ dev_p7_db ( bp, idx, ( u32 )bp->rx_ring_id, DBC_DBC_TYPE_SRQ,
+ ( u32 )bp->rx.epoch, 0 );
+ else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
+ dev_p5_db ( bp, idx, ( u32 )bp->rx_ring_id, DBC_DBC_TYPE_SRQ );
else
write32 ( RX_DOORBELL_KEY_RX | idx, ( bp->bar1 + 0 ) );
}
static void bnxt_db_tx ( struct bnxt *bp, u32 idx )
{
- if ( bp->thor )
- thor_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ );
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
+ dev_p7_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ,
+ ( u32 )bp->tx.epoch, 0 );
+ else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
+ dev_p5_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ );
else
write32 ( ( u32 ) ( TX_DOORBELL_KEY_TX | idx ),
( bp->bar1 + 0 ) );
@@ -253,6 +282,31 @@ static u16 bnxt_get_pkt_vlan ( char *src )
return 0;
}
+static u16 bnxt_get_rx_vlan ( struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi )
+{
+ struct rx_pkt_v3_cmpl *rx_cmp_v3 = ( struct rx_pkt_v3_cmpl * )rx_cmp;
+ struct rx_pkt_v3_cmpl_hi *rx_cmp_hi_v3 = ( struct rx_pkt_v3_cmpl_hi * )rx_cmp_hi;
+ u16 rx_vlan;
+
+ /* Get VLAN ID from RX completion ring */
+ if ( ( rx_cmp_v3->flags_type & RX_PKT_V3_CMPL_TYPE_MASK ) ==
+ RX_PKT_V3_CMPL_TYPE_RX_L2_V3 ) {
+ if ( rx_cmp_hi_v3->flags2 & RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR )
+ rx_vlan = ( rx_cmp_hi_v3->metadata0 &
+ RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK );
+ else
+ rx_vlan = 0;
+ } else {
+ if ( rx_cmp_hi->flags2 & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN )
+ rx_vlan = ( rx_cmp_hi->metadata &
+ RX_PKT_CMPL_METADATA_VID_MASK );
+ else
+ rx_vlan = 0;
+ }
+
+ return rx_vlan;
+}
+
int bnxt_vlan_drop ( struct bnxt *bp, u16 rx_vlan )
{
if ( rx_vlan ) {
@@ -382,6 +436,9 @@ int bnxt_post_rx_buffers ( struct bnxt *bp )
}
}
cons_id = NEXT_IDX ( cons_id, bp->rx.ring_cnt );
+ /* If the ring has wrapped, flip the epoch bit */
+ if ( iob_idx > cons_id )
+ bp->rx.epoch ^= 1;
bp->rx.iob_cnt++;
}
@@ -396,14 +453,21 @@ int bnxt_post_rx_buffers ( struct bnxt *bp )
}
u8 bnxt_rx_drop ( struct bnxt *bp, struct io_buffer *iob,
+ struct rx_pkt_cmpl *rx_cmp,
struct rx_pkt_cmpl_hi *rx_cmp_hi, u16 rx_len )
{
+ struct rx_pkt_v3_cmpl *rx_cmp_v3 = ( struct rx_pkt_v3_cmpl * )rx_cmp;
+ struct rx_pkt_v3_cmpl_hi *rx_cmp_hi_v3 = ( struct rx_pkt_v3_cmpl_hi * )rx_cmp_hi;
u8 *rx_buf = ( u8 * )iob->data;
u16 err_flags, rx_vlan;
u8 ignore_chksum_err = 0;
int i;
- err_flags = rx_cmp_hi->errors_v2 >> RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT;
+ if ( ( rx_cmp_v3->flags_type & RX_PKT_V3_CMPL_TYPE_MASK ) ==
+ RX_PKT_V3_CMPL_TYPE_RX_L2_V3 ) {
+ err_flags = rx_cmp_hi_v3->errors_v2 >> RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT;
+ } else
+ err_flags = rx_cmp_hi->errors_v2 >> RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT;
if ( rx_cmp_hi->errors_v2 == 0x20 || rx_cmp_hi->errors_v2 == 0x21 )
ignore_chksum_err = 1;
@@ -423,13 +487,7 @@ u8 bnxt_rx_drop ( struct bnxt *bp, struct io_buffer *iob,
return 2;
}
- /* Get VLAN ID from RX completion ring */
- if ( rx_cmp_hi->flags2 & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN )
- rx_vlan = ( rx_cmp_hi->metadata &
- RX_PKT_CMPL_METADATA_VID_MASK );
- else
- rx_vlan = 0;
-
+ rx_vlan = bnxt_get_rx_vlan ( rx_cmp, rx_cmp_hi );
dbg_rx_vlan ( bp, rx_cmp_hi->metadata, rx_cmp_hi->flags2, rx_vlan );
if ( bnxt_vlan_drop ( bp, rx_vlan ) ) {
bp->rx.drop_vlan++;
@@ -449,10 +507,11 @@ static void bnxt_adv_cq_index ( struct bnxt *bp, u16 cnt )
u16 cons_id;
cons_id = bp->cq.cons_id + cnt;
- if ( cons_id >= MAX_CQ_DESC_CNT ) {
+ if ( cons_id >= bp->cq.ring_cnt) {
/* Toggle completion bit when the ring wraps. */
bp->cq.completion_bit ^= 1;
- cons_id = cons_id - MAX_CQ_DESC_CNT;
+ bp->cq.epoch ^= 1;
+ cons_id = cons_id - bp->cq.ring_cnt;
}
bp->cq.cons_id = cons_id;
}
@@ -466,7 +525,7 @@ void bnxt_rx_process ( struct net_device *dev, struct bnxt *bp,
dump_rx_bd ( rx_cmp, rx_cmp_hi, desc_idx );
assert ( !iob );
- drop = bnxt_rx_drop ( bp, iob, rx_cmp_hi, rx_cmp->len );
+ drop = bnxt_rx_drop ( bp, iob, rx_cmp, rx_cmp_hi, rx_cmp->len );
dbg_rxp ( iob->data, rx_cmp->len, drop );
if ( drop )
netdev_rx_err ( dev, iob, -EINVAL );
@@ -531,12 +590,17 @@ void bnxt_mm_nic ( struct bnxt *bp )
memset ( bp->nq.bd_virt, 0, NQ_RING_BUFFER_SIZE );
bp->nq.cons_id = 0;
bp->nq.completion_bit = 0x1;
+ bp->nq.epoch = 0;
+ bp->nq.toggle = 0;
bp->cq.cons_id = 0;
bp->cq.completion_bit = 0x1;
+ bp->cq.epoch = 0;
bp->tx.prod_id = 0;
bp->tx.cons_id = 0;
+ bp->tx.epoch = 0;
bp->rx.cons_id = 0;
bp->rx.iob_cnt = 0;
+ bp->rx.epoch = 0;
bp->link_status = STATUS_LINK_DOWN;
bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
@@ -722,8 +786,16 @@ static int bnxt_hwrm_ver_get ( struct bnxt *bp )
( resp->dev_caps_cfg & SHORT_CMD_REQUIRED ) )
FLAG_SET ( bp->flags, BNXT_FLAG_HWRM_SHORT_CMD_SUPP );
bp->hwrm_max_ext_req_len = resp->max_ext_req_len;
- if ( bp->chip_num == CHIP_NUM_57500 )
- bp->thor = 1;
+ if ( ( bp->chip_num == CHIP_NUM_57508 ) ||
+ ( bp->chip_num == CHIP_NUM_57504 ) ||
+ ( bp->chip_num == CHIP_NUM_57502 ) ) {
+ FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5 );
+ FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS );
+ }
+ if ( bp->chip_num == CHIP_NUM_57608 ) {
+ FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P7 );
+ FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS );
+ }
dbg_fw_ver ( resp, bp->hwrm_cmd_timeout );
return STATUS_SUCCESS;
}
@@ -915,6 +987,30 @@ static int bnxt_hwrm_func_qcfg_req ( struct bnxt *bp )
return STATUS_SUCCESS;
}
+static int bnxt_hwrm_port_phy_qcaps_req ( struct bnxt *bp )
+{
+ u16 cmd_len = ( u16 )sizeof ( struct hwrm_port_phy_qcaps_input );
+ struct hwrm_port_phy_qcaps_input *req;
+ struct hwrm_port_phy_qcaps_output *resp;
+ int rc;
+
+ DBGP ( "%s\n", __func__ );
+
+ req = ( struct hwrm_port_phy_qcaps_input * )bp->hwrm_addr_req;
+ resp = ( struct hwrm_port_phy_qcaps_output * )bp->hwrm_addr_resp;
+ hwrm_init ( bp, ( void * )req, ( u16 )HWRM_PORT_PHY_QCAPS, cmd_len );
+ rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
+ if ( rc ) {
+ DBGP ( "-s %s ( ): Failed\n", __func__ );
+ return STATUS_FAILURE;
+ }
+
+ if ( resp->flags2 & PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED )
+ FLAG_SET ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 );
+
+ return STATUS_SUCCESS;
+}
+
static int bnxt_hwrm_func_reset_req ( struct bnxt *bp )
{
u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_reset_input );
@@ -942,7 +1038,7 @@ static int bnxt_hwrm_func_cfg_req ( struct bnxt *bp )
hwrm_init ( bp, ( void * )req, ( u16 )HWRM_FUNC_CFG, cmd_len );
req->fid = ( u16 )HWRM_NA_SIGNATURE;
bnxt_hwrm_assign_resources ( bp );
- if ( bp->thor ) {
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) {
req->enables |= ( FUNC_CFG_REQ_ENABLES_NUM_MSIX |
FUNC_CFG_REQ_ENABLES_NUM_VNICS |
FUNC_CFG_REQ_ENABLES_EVB_MODE );
@@ -1009,7 +1105,7 @@ static int bnxt_hwrm_set_async_event ( struct bnxt *bp )
u16 idx;
DBGP ( "%s\n", __func__ );
- if ( bp->thor )
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) )
idx = bp->nq_ring_id;
else
idx = bp->cq_ring_id;
@@ -1160,6 +1256,10 @@ static int bnxt_hwrm_port_phy_qcfg ( struct bnxt *bp, u16 idx )
if ( idx & SUPPORT_SPEEDS )
bp->support_speeds = resp->support_speeds;
+ if ( idx & SUPPORT_SPEEDS2 )
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) )
+ bp->auto_link_speeds2_mask = resp->auto_link_speeds2;
+
if ( idx & DETECT_MEDIA )
bp->media_detect = resp->module_status;
@@ -1199,22 +1299,24 @@ static int bnxt_get_link_speed ( struct bnxt *bp )
u32 *ptr32 = ( u32 * )bp->hwrm_addr_dma;
DBGP ( "%s\n", __func__ );
- test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
- ( u16 )LINK_SPEED_DRV_NUM,
- 1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
- return STATUS_FAILURE;
- bp->link_set = SET_LINK ( *ptr32, SPEED_DRV_MASK, SPEED_DRV_SHIFT );
+ if ( ! ( FLAG_TEST (bp->flags, BNXT_FLAG_IS_CHIP_P7 ) ) ) {
+ test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
+ ( u16 )LINK_SPEED_DRV_NUM,
+ 1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
+ return STATUS_FAILURE;
+ bp->link_set = SET_LINK ( *ptr32, SPEED_DRV_MASK, SPEED_DRV_SHIFT );
+ test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
+ ( u16 )D3_LINK_SPEED_FW_NUM, 1,
+ ( u16 )bp->port_idx ) != STATUS_SUCCESS )
+ return STATUS_FAILURE;
+ bp->link_set |= SET_LINK ( *ptr32, D3_SPEED_FW_MASK,
+ D3_SPEED_FW_SHIFT );
+ }
test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
( u16 )LINK_SPEED_FW_NUM,
1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
return STATUS_FAILURE;
bp->link_set |= SET_LINK ( *ptr32, SPEED_FW_MASK, SPEED_FW_SHIFT );
- test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
- ( u16 )D3_LINK_SPEED_FW_NUM, 1,
- ( u16 )bp->port_idx ) != STATUS_SUCCESS )
- return STATUS_FAILURE;
- bp->link_set |= SET_LINK ( *ptr32, D3_SPEED_FW_MASK,
- D3_SPEED_FW_SHIFT );
test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 1,
( u16 )PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM,
1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
@@ -1222,32 +1324,51 @@ static int bnxt_get_link_speed ( struct bnxt *bp )
bp->link_set |= SET_LINK ( *ptr32,
MEDIA_AUTO_DETECT_MASK, MEDIA_AUTO_DETECT_SHIFT );
- switch ( bp->link_set & LINK_SPEED_DRV_MASK ) {
- case LINK_SPEED_DRV_1G:
+ /* Use LINK_SPEED_FW_xxx which is valid for CHIP_P7 and earlier devices */
+ switch ( bp->link_set & LINK_SPEED_FW_MASK ) {
+ case LINK_SPEED_FW_1G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_1000MBPS );
break;
- case LINK_SPEED_DRV_2_5G:
+ case LINK_SPEED_FW_2_5G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_2500MBPS );
break;
- case LINK_SPEED_DRV_10G:
+ case LINK_SPEED_FW_10G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_10GBPS );
break;
- case LINK_SPEED_DRV_25G:
+ case LINK_SPEED_FW_25G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_25GBPS );
break;
- case LINK_SPEED_DRV_40G:
+ case LINK_SPEED_FW_40G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_40GBPS );
break;
- case LINK_SPEED_DRV_50G:
+ case LINK_SPEED_FW_50G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_50GBPS );
break;
- case LINK_SPEED_DRV_100G:
+ case LINK_SPEED_FW_50G_PAM4:
+ bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_50PAM4GBPS );
+ break;
+ case LINK_SPEED_FW_100G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_100GBPS );
break;
- case LINK_SPEED_DRV_200G:
+ case LINK_SPEED_FW_100G_PAM4:
+ bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_100PAM4GBPS );
+ break;
+ case LINK_SPEED_FW_100G_PAM4_112:
+ bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_100PAM4_112GBPS );
+ break;
+ case LINK_SPEED_FW_200G:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_200GBPS );
break;
- case LINK_SPEED_DRV_AUTONEG:
+ case LINK_SPEED_FW_200G_PAM4_112:
+ bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_200PAM4_112GBPS );
+ break;
+ case LINK_SPEED_FW_400G_PAM4:
+ bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_400PAM4GBPS );
+ break;
+ case LINK_SPEED_FW_400G_PAM4_112:
+ bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_400PAM4_112GBPS );
+ break;
+ case LINK_SPEED_FW_AUTONEG:
bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_AUTONEG );
break;
default:
@@ -1266,27 +1387,29 @@ static int bnxt_get_vlan ( struct bnxt *bp )
if ( bp->vf )
return STATUS_SUCCESS;
- test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 1,
- ( u16 )FUNC_CFG_PRE_BOOT_MBA_VLAN_NUM, 1,
- ( u16 )bp->ordinal_value ) != STATUS_SUCCESS )
- return STATUS_FAILURE;
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) ) ) {
+ test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 1,
+ ( u16 )FUNC_CFG_PRE_BOOT_MBA_VLAN_NUM, 1,
+ ( u16 )bp->ordinal_value ) != STATUS_SUCCESS )
+ return STATUS_FAILURE;
- bp->mba_cfg2 = SET_MBA ( *ptr32, VLAN_MASK, VLAN_SHIFT );
- test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 16,
- ( u16 )FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_NUM, 1,
- ( u16 )bp->ordinal_value ) != STATUS_SUCCESS )
- return STATUS_FAILURE;
+ bp->mba_cfg2 = SET_MBA ( *ptr32, VLAN_MASK, VLAN_SHIFT );
+ test_if ( bnxt_hwrm_nvm_get_variable_req ( bp, 16,
+ ( u16 )FUNC_CFG_PRE_BOOT_MBA_VLAN_VALUE_NUM, 1,
+ ( u16 )bp->ordinal_value ) != STATUS_SUCCESS )
+ return STATUS_FAILURE;
- bp->mba_cfg2 |= SET_MBA ( *ptr32, VLAN_VALUE_MASK, VLAN_VALUE_SHIFT );
- if ( bp->mba_cfg2 & FUNC_CFG_PRE_BOOT_MBA_VLAN_ENABLED )
- bp->vlan_id = bp->mba_cfg2 & VLAN_VALUE_MASK;
- else
- bp->vlan_id = 0;
+ bp->mba_cfg2 |= SET_MBA ( *ptr32, VLAN_VALUE_MASK, VLAN_VALUE_SHIFT );
+ if ( bp->mba_cfg2 & FUNC_CFG_PRE_BOOT_MBA_VLAN_ENABLED )
+ bp->vlan_id = bp->mba_cfg2 & VLAN_VALUE_MASK;
+ else
+ bp->vlan_id = 0;
- if ( bp->mba_cfg2 & FUNC_CFG_PRE_BOOT_MBA_VLAN_ENABLED )
- DBGP ( "VLAN MBA Enabled ( %d )\n",
- ( bp->mba_cfg2 & VLAN_VALUE_MASK ) );
+ if ( bp->mba_cfg2 & FUNC_CFG_PRE_BOOT_MBA_VLAN_ENABLED )
+ DBGP ( "VLAN MBA Enabled ( %d )\n",
+ ( bp->mba_cfg2 & VLAN_VALUE_MASK ) );
+ }
return STATUS_SUCCESS;
}
@@ -1296,7 +1419,7 @@ static int bnxt_hwrm_backing_store_qcfg ( struct bnxt *bp )
struct hwrm_func_backing_store_qcfg_input *req;
DBGP ( "%s\n", __func__ );
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
return STATUS_SUCCESS;
req = ( struct hwrm_func_backing_store_qcfg_input * )bp->hwrm_addr_req;
@@ -1311,7 +1434,7 @@ static int bnxt_hwrm_backing_store_cfg ( struct bnxt *bp )
struct hwrm_func_backing_store_cfg_input *req;
DBGP ( "%s\n", __func__ );
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
return STATUS_SUCCESS;
req = ( struct hwrm_func_backing_store_cfg_input * )bp->hwrm_addr_req;
@@ -1330,7 +1453,7 @@ static int bnxt_hwrm_queue_qportcfg ( struct bnxt *bp )
int rc;
DBGP ( "%s\n", __func__ );
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
return STATUS_SUCCESS;
req = ( struct hwrm_queue_qportcfg_input * )bp->hwrm_addr_req;
@@ -1370,7 +1493,10 @@ static int bnxt_hwrm_port_phy_cfg ( struct bnxt *bp )
u32 flags;
u32 enables = 0;
u16 force_link_speed = 0;
+ u16 force_link_speeds2 = 0;
+ u16 force_pam4_link_speed = 0;
u16 auto_link_speed_mask = 0;
+ u16 auto_link_speeds2_mask = 0;
u8 auto_mode = 0;
u8 auto_pause = 0;
u8 auto_duplex = 0;
@@ -1385,34 +1511,111 @@ static int bnxt_hwrm_port_phy_cfg ( struct bnxt *bp )
force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
break;
case MEDIUM_SPEED_10GBPS:
- force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
+ }
break;
case MEDIUM_SPEED_25GBPS:
- force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
+ }
break;
case MEDIUM_SPEED_40GBPS:
- force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
+ }
break;
case MEDIUM_SPEED_50GBPS:
- force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
+ }
+ break;
+ case MEDIUM_SPEED_50PAM4GBPS:
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_pam4_link_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED;
+ }
break;
case MEDIUM_SPEED_100GBPS:
- force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
+ }
+ break;
+ case MEDIUM_SPEED_100PAM4GBPS:
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_pam4_link_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED;
+ }
+ break;
+ case MEDIUM_SPEED_100PAM4_112GBPS:
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ }
break;
case MEDIUM_SPEED_200GBPS:
- force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB;
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ } else {
+ force_pam4_link_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED;
+ }
+ break;
+ case MEDIUM_SPEED_200PAM4_112GBPS:
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ }
+ break;
+ case MEDIUM_SPEED_400PAM4GBPS:
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ }
break;
+ case MEDIUM_SPEED_400PAM4_112GBPS:
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
+ force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112;
+ enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
+ }
+ break;
default:
auto_mode = PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
flags &= ~PORT_PHY_CFG_REQ_FLAGS_FORCE;
enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE |
- PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK |
PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX |
PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE;
+ if ( FLAG_TEST (bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) )
+ enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK;
+ else
+ enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK;
auto_pause = PORT_PHY_CFG_REQ_AUTO_PAUSE_TX |
PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH;
auto_link_speed_mask = bp->support_speeds;
+ auto_link_speeds2_mask = bp->auto_link_speeds2_mask;
break;
}
@@ -1421,10 +1624,13 @@ static int bnxt_hwrm_port_phy_cfg ( struct bnxt *bp )
req->enables = enables;
req->port_id = bp->port_idx;
req->force_link_speed = force_link_speed;
+ req->force_pam4_link_speed = force_pam4_link_speed;
+ req->force_link_speeds2 = force_link_speeds2;
req->auto_mode = auto_mode;
req->auto_duplex = auto_duplex;
req->auto_pause = auto_pause;
req->auto_link_speed_mask = auto_link_speed_mask;
+ req->auto_link_speeds2_mask = auto_link_speeds2_mask;
return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
}
@@ -1563,7 +1769,7 @@ static int bnxt_hwrm_ring_alloc_grp ( struct bnxt *bp )
int rc;
DBGP ( "%s\n", __func__ );
- if ( bp->thor )
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) )
return STATUS_SUCCESS;
req = ( struct hwrm_ring_grp_alloc_input * )bp->hwrm_addr_req;
@@ -1614,7 +1820,7 @@ static int bnxt_hwrm_ring_alloc ( struct bnxt *bp, u8 type )
switch ( type ) {
case RING_ALLOC_REQ_RING_TYPE_NQ:
req->page_size = LM_PAGE_BITS ( 12 );
- req->int_mode = BNXT_CQ_INTR_MODE ( bp->vf );
+ req->int_mode = BNXT_CQ_INTR_MODE ( ( (FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7) ) || bp->vf ) );
req->length = ( u32 )bp->nq.ring_cnt;
req->logical_id = 0xFFFF; // Required value for Thor FW?
req->page_tbl_addr = virt_to_bus ( bp->nq.bd_virt );
@@ -1624,7 +1830,7 @@ static int bnxt_hwrm_ring_alloc ( struct bnxt *bp, u8 type )
req->int_mode = BNXT_CQ_INTR_MODE ( bp->vf );
req->length = ( u32 )bp->cq.ring_cnt;
req->page_tbl_addr = virt_to_bus ( bp->cq.bd_virt );
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
break;
req->enables = RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID;
req->nq_ring_id = bp->nq_ring_id;
@@ -1646,7 +1852,7 @@ static int bnxt_hwrm_ring_alloc ( struct bnxt *bp, u8 type )
req->stat_ctx_id = ( u32 )STAT_CTX_ID;
req->cmpl_ring_id = bp->cq_ring_id;
req->page_tbl_addr = virt_to_bus ( bp->rx.bd_virt );
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
break;
req->queue_id = ( u16 )RX_RING_QID;
req->rx_buf_size = MAX_ETHERNET_PACKET_BUFFER_SIZE;
@@ -1742,7 +1948,7 @@ static int bnxt_hwrm_ring_free_rx ( struct bnxt *bp )
static int bnxt_hwrm_ring_alloc_nq ( struct bnxt *bp )
{
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
return STATUS_SUCCESS;
return bnxt_hwrm_ring_alloc ( bp, RING_ALLOC_REQ_RING_TYPE_NQ );
}
@@ -1751,7 +1957,7 @@ static int bnxt_hwrm_ring_free_nq ( struct bnxt *bp )
{
int ret = STATUS_SUCCESS;
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
return STATUS_SUCCESS;
DBGP ( "%s\n", __func__ );
@@ -1822,7 +2028,7 @@ static int bnxt_hwrm_vnic_cfg ( struct bnxt *bp )
req->enables = VNIC_CFG_REQ_ENABLES_MRU;
req->mru = bp->mtu;
- if ( bp->thor ) {
+ if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) {
req->enables |= ( VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID );
req->default_rx_ring_id = bp->rx_ring_id;
@@ -1876,6 +2082,7 @@ hwrm_func_t bring_up_chip[] = {
bnxt_hwrm_backing_store_cfg, /* HWRM_FUNC_BACKING_STORE_CFG */
bnxt_hwrm_backing_store_qcfg, /* HWRM_FUNC_BACKING_STORE_QCFG */
bnxt_hwrm_func_resource_qcaps, /* HWRM_FUNC_RESOURCE_QCAPS */
+ bnxt_hwrm_port_phy_qcaps_req, /* HWRM_PORT_PHY_QCAPS */
bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
bnxt_get_vlan, /* HWRM_NVM_GET_VARIABLE - vlan */
bnxt_hwrm_port_mac_cfg, /* HWRM_PORT_MAC_CFG */
@@ -1968,6 +2175,9 @@ static int bnxt_tx ( struct net_device *dev, struct io_buffer *iob )
bp->tx.iob[entry] = iob;
bnxt_set_txq ( bp, entry, mapping, len );
entry = NEXT_IDX ( entry, bp->tx.ring_cnt );
+ /* If the ring has wrapped, toggle the epoch bit */
+ if ( bp->tx.prod_id > entry )
+ bp->tx.epoch ^= 1;
dump_tx_pkt ( ( u8 * )iob->data, len, bp->tx.prod_id );
/* Packets are ready, update Tx producer idx local and on card. */
bnxt_db_tx ( bp, ( u32 )entry );
@@ -1986,6 +2196,7 @@ static void bnxt_adv_nq_index ( struct bnxt *bp, u16 cnt )
if ( cons_id >= bp->nq.ring_cnt ) {
/* Toggle completion bit when the ring wraps. */
bp->nq.completion_bit ^= 1;
+ bp->nq.epoch ^= 1;
cons_id = cons_id - bp->nq.ring_cnt;
}
bp->nq.cons_id = cons_id;
@@ -2026,7 +2237,7 @@ static void bnxt_service_cq ( struct net_device *dev )
cq_type = cmp->type & CMPL_BASE_TYPE_MASK;
dump_evt ( ( u8 * )cmp, cq_type, bp->cq.cons_id, 0 );
- dump_cq ( cmp, bp->cq.cons_id );
+ dump_cq ( cmp, bp->cq.cons_id, bp->nq.toggle );
switch ( cq_type ) {
case CMPL_BASE_TYPE_TX_L2:
@@ -2037,6 +2248,7 @@ static void bnxt_service_cq ( struct net_device *dev )
bnxt_adv_cq_index ( bp, 1 );
break;
case CMPL_BASE_TYPE_RX_L2:
+ case CMPL_BASE_TYPE_RX_L2_V3:
done = bnxt_rx_complete ( dev,
( struct rx_pkt_cmpl * )cmp );
break;
@@ -2063,7 +2275,7 @@ static void bnxt_service_nq ( struct net_device *dev )
int done = SERVICE_NEXT_NQ_BD;
u32 nq_type;
- if ( !bp->thor )
+ if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
return;
while ( done == SERVICE_NEXT_NQ_BD ) {
@@ -2072,6 +2284,7 @@ static void bnxt_service_nq ( struct net_device *dev )
if ( ( nqp->v & NQ_CN_V ) ^ bp->nq.completion_bit )
break;
nq_type = ( nqp->type & NQ_CN_TYPE_MASK );
+ bp->nq.toggle = ( ( nqp->type & NQ_CN_TOGGLE_MASK ) >> NQ_CN_TOGGLE_SFT );
dump_evt ( ( u8 * )nqp, nq_type, bp->nq.cons_id, 1 );
dump_nq ( nqp, bp->nq.cons_id );
@@ -2096,8 +2309,8 @@ static void bnxt_service_nq ( struct net_device *dev )
static void bnxt_poll ( struct net_device *dev )
{
mb ( );
- bnxt_service_cq ( dev );
bnxt_service_nq ( dev );
+ bnxt_service_cq ( dev );
}
static void bnxt_close ( struct net_device *dev )
diff --git a/src/drivers/net/bnxt/bnxt.h b/src/drivers/net/bnxt/bnxt.h
index 2cbaec5e..8c8a3328 100644
--- a/src/drivers/net/bnxt/bnxt.h
+++ b/src/drivers/net/bnxt/bnxt.h
@@ -52,6 +52,10 @@ union dma_addr64_t {
#define BNXT_FLAG_NPAR_MODE 0x0010
#define BNXT_FLAG_ATOMICS_ENABLE 0x0020
#define BNXT_FLAG_PCI_VF 0x0040
+#define BNXT_FLAG_LINK_SPEEDS2 0x0080
+#define BNXT_FLAG_IS_CHIP_P5 0x0100
+#define BNXT_FLAG_IS_CHIP_P5_PLUS 0x0200
+#define BNXT_FLAG_IS_CHIP_P7 0x0400
/*******************************************************************************
* Status codes.
******************************************************************************/
@@ -106,6 +110,12 @@ union dma_addr64_t {
#define MEDIUM_SPEED_50GBPS 0x0a00L
#define MEDIUM_SPEED_100GBPS 0x0b00L
#define MEDIUM_SPEED_200GBPS 0x0c00L
+#define MEDIUM_SPEED_50PAM4GBPS 0x0d00L
+#define MEDIUM_SPEED_100PAM4GBPS 0x0e00L
+#define MEDIUM_SPEED_100PAM4_112GBPS 0x0f00L
+#define MEDIUM_SPEED_200PAM4_112GBPS 0x1000L
+#define MEDIUM_SPEED_400PAM4GBPS 0x2000L
+#define MEDIUM_SPEED_400PAM4_112GBPS 0x3000L
#define MEDIUM_SPEED_AUTONEG_1G_FALLBACK 0x8000L /* Serdes */
#define MEDIUM_SPEED_AUTONEG_2_5G_FALLBACK 0x8100L /* Serdes */
#define MEDIUM_SPEED_HARDWARE_DEFAULT 0xff00L /* Serdes nvram def.*/
@@ -168,9 +178,9 @@ union dma_addr64_t {
RX_MASK_ACCEPT_MULTICAST)
#define MAX_NQ_DESC_CNT 64
#define NQ_RING_BUFFER_SIZE (MAX_NQ_DESC_CNT * sizeof(struct cmpl_base))
-#define TX_RING_QID (bp->thor ? (u16)bp->queue_id : ((u16)bp->port_idx * 10))
-#define RX_RING_QID (bp->thor ? bp->queue_id : 0)
-#define STAT_CTX_ID ((bp->vf || bp->thor) ? bp->stat_ctx_id : 0)
+#define TX_RING_QID (FLAG_TEST(bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS) ? (u16)bp->queue_id : ((u16)bp->port_idx * 10))
+#define RX_RING_QID (FLAG_TEST(bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS) ? bp->queue_id : 0)
+#define STAT_CTX_ID ((bp->vf || FLAG_TEST(bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS)) ? bp->stat_ctx_id : 0)
#define TX_AVAIL(r) (r - 1)
#define TX_IN_USE(a, b, c) ((a - b) & (c - 1))
#define NO_MORE_NQ_BD_TO_SERVICE 1
@@ -189,13 +199,19 @@ union dma_addr64_t {
((idx) << DBC_DBC_INDEX_SFT) & DBC_DBC_INDEX_MASK)
#define DBC_MSG_XID(xid, flg) (\
(((xid) << DBC_DBC_XID_SFT) & DBC_DBC_XID_MASK) | \
- DBC_DBC_PATH_L2 | (flg))
+ DBC_DBC_PATH_L2 | (FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) ? DBC_DBC_VALID : 0) | (flg))
+#define DBC_MSG_EPCH(idx) (\
+ ((idx) << DBC_DBC_EPOCH_SFT))
+#define DBC_MSG_TOGGLE(idx) (\
+ ((idx) << DBC_DBC_TOGGLE_SFT) & DBC_DBC_TOGGLE_MASK)
#define PHY_STATUS 0x0001
#define PHY_SPEED 0x0002
#define DETECT_MEDIA 0x0004
#define SUPPORT_SPEEDS 0x0008
+#define SUPPORT_SPEEDS2 0x0010
#define QCFG_PHY_ALL (\
- SUPPORT_SPEEDS | DETECT_MEDIA | PHY_SPEED | PHY_STATUS)
+ SUPPORT_SPEEDS | SUPPORT_SPEEDS2 | \
+ DETECT_MEDIA | PHY_SPEED | PHY_STATUS)
#define str_mbps "Mbps"
#define str_gbps "Gbps"
/*
@@ -287,6 +303,18 @@ union dma_addr64_t {
#define NS_LINK_SPEED_FW_100G (0x6)
#define LINK_SPEED_FW_200G (0x7L << 7)
#define NS_LINK_SPEED_FW_200G (0x7)
+#define LINK_SPEED_FW_50G_PAM4 (0x8L << 7)
+#define NS_LINK_SPEED_FW_50G_PAM4 (0x8)
+#define LINK_SPEED_FW_100G_PAM4 (0x9L << 7)
+#define NS_LINK_SPEED_FW_100G_PAM4 (0x9)
+#define LINK_SPEED_FW_100G_PAM4_112 (0xAL << 7)
+#define NS_LINK_SPEED_FW_100G_PAM4_112 (0xA)
+#define LINK_SPEED_FW_200G_PAM4_112 (0xBL << 7)
+#define NS_LINK_SPEED_FW_200G_PAM4_112 (0xB)
+#define LINK_SPEED_FW_400G_PAM4 (0xCL << 7)
+#define NS_LINK_SPEED_FW_400G_PAM4 (0xC)
+#define LINK_SPEED_FW_400G_PAM4_112 (0xDL << 7)
+#define NS_LINK_SPEED_FW_400G_PAM4_112 (0xD)
#define LINK_SPEED_FW_2_5G (0xEL << 7)
#define NS_LINK_SPEED_FW_2_5G (0xE)
#define LINK_SPEED_FW_100M (0xFL << 7)
@@ -387,6 +415,10 @@ struct dbc_dbc {
__le32 index;
#define DBC_DBC_INDEX_MASK 0xffffffUL
#define DBC_DBC_INDEX_SFT 0
+ #define DBC_DBC_EPOCH 0x1000000UL
+ #define DBC_DBC_EPOCH_SFT 24
+ #define DBC_DBC_TOGGLE_MASK 0x6000000UL
+ #define DBC_DBC_TOGGLE_SFT 25
__le32 type_path_xid;
#define DBC_DBC_XID_MASK 0xfffffUL
#define DBC_DBC_XID_SFT 0
@@ -396,6 +428,7 @@ struct dbc_dbc {
#define DBC_DBC_PATH_L2 (0x1UL << 24)
#define DBC_DBC_PATH_ENGINE (0x2UL << 24)
#define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE
+ #define DBC_DBC_VALID 0x4000000UL
#define DBC_DBC_DEBUG_TRACE 0x8000000UL
#define DBC_DBC_TYPE_MASK 0xf0000000UL
#define DBC_DBC_TYPE_SFT 28
@@ -481,6 +514,8 @@ struct tx_info {
u16 ring_cnt;
u32 cnt; /* Tx statistics. */
u32 cnt_req;
+ u8 epoch;
+ u8 res[3];
};
struct cmpl_base {
@@ -492,6 +527,7 @@ struct cmpl_base {
#define CMPL_BASE_TYPE_RX_AGG 0x12UL
#define CMPL_BASE_TYPE_RX_TPA_START 0x13UL
#define CMPL_BASE_TYPE_RX_TPA_END 0x15UL
+#define CMPL_BASE_TYPE_RX_L2_V3 0x17UL
#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
#define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
#define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
@@ -517,7 +553,8 @@ struct cmp_info {
u16 cons_id;
u16 ring_cnt;
u8 completion_bit;
- u8 res[3];
+ u8 epoch;
+ u8 res[2];
};
/* Completion Queue Notification */
@@ -533,6 +570,8 @@ struct nq_base {
*/
#define NQ_CN_TYPE_MASK 0x3fUL
#define NQ_CN_TYPE_SFT 0
+#define NQ_CN_TOGGLE_MASK 0xc0UL
+#define NQ_CN_TOGGLE_SFT 6
/* CQ Notification */
#define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
#define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
@@ -561,7 +600,9 @@ struct nq_info {
u16 cons_id;
u16 ring_cnt;
u8 completion_bit;
- u8 res[3];
+ u8 epoch;
+ u8 toggle;
+ u8 res[1];
};
struct rx_pkt_cmpl {
@@ -675,6 +716,156 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_REORDER_SFT 0
};
+struct rx_pkt_v3_cmpl {
+ u16 flags_type;
+ #define RX_PKT_V3_CMPL_TYPE_MASK 0x3fUL
+ #define RX_PKT_V3_CMPL_TYPE_SFT 0
+ /*
+ * RX L2 V3 completion:
+ * Completion of and L2 RX packet. Length = 32B
+ * This is the new version of the RX_L2 completion used in Thor2
+ * and later chips.
+ */
+ #define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 0x17UL
+ #define RX_PKT_V3_CMPL_TYPE_LAST RX_PKT_V3_CMPL_TYPE_RX_L2_V3
+ #define RX_PKT_V3_CMPL_FLAGS_MASK 0xffc0UL
+ #define RX_PKT_V3_CMPL_FLAGS_SFT 6
+ #define RX_PKT_V3_CMPL_FLAGS_ERROR 0x40UL
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK 0x380UL
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_SFT 7
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL (0x0UL << 7)
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO (0x1UL << 7)
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS (0x2UL << 7)
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION (0x3UL << 7)
+ #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION
+ #define RX_PKT_V3_CMPL_FLAGS_RSS_VALID 0x400UL
+ #define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT 0x800UL
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK 0xf000UL
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_SFT 12
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP (0x1UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP (0x2UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP (0x3UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE (0x4UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE (0x5UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP (0x7UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 12)
+ #define RX_PKT_V3_CMPL_FLAGS_ITYPE_LAST RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
+ u16 len;
+ u32 opaque;
+ u16 rss_hash_type_agg_bufs_v1;
+ #define RX_PKT_V3_CMPL_V1 0x1UL
+ #define RX_PKT_V3_CMPL_AGG_BUFS_MASK 0x3eUL
+ #define RX_PKT_V3_CMPL_AGG_BUFS_SFT 1
+ #define RX_PKT_V3_CMPL_UNUSED1 0x40UL
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK 0xff80UL
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_SFT 7
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (0x0UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (0x1UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (0x3UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (0x4UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (0x5UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (0x6UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (0x7UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (0x8UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (0x9UL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (0xaUL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (0xbUL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (0xcUL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (0xdUL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (0xeUL << 7)
+ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14
+ u16 metadata1_payload_offset;
+ #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK 0x1ffUL
+ #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT 0
+ #define RX_PKT_V3_CMPL_METADATA1_MASK 0xf000UL
+ #define RX_PKT_V3_CMPL_METADATA1_SFT 12
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK 0x7000UL
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_SFT 12
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 12)
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 (0x1UL << 12)
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 (0x2UL << 12)
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 (0x3UL << 12)
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 (0x4UL << 12)
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 12)
+ #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_LAST RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG
+ #define RX_PKT_V3_CMPL_METADATA1_VALID 0x8000UL
+ u32 rss_hash;
+};
+
+struct rx_pkt_v3_cmpl_hi {
+ u32 flags2;
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC 0x1UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC 0x2UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC 0x4UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC 0x8UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK 0xf0UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_LAST RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE 0x100UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE 0x400UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 (0x0UL << 10)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 (0x1UL << 10)
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_LAST RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
+ #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
+ u32 metadata2;
+ u16 errors_v2;
+ #define RX_PKT_V3_CMPL_HI_V2 0x1UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_MASK 0xfffeUL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_SFT 1
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK 0xeUL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2UL << 1)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
+ #define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR 0x10UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR 0x20UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR 0x40UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR 0x80UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR 0x100UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK 0xe00UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x3UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x4UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x5UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (0x6UL << 9)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK 0xf000UL
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
+ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
+ u16 metadata0;
+ #define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK 0xfffUL
+ #define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0
+ #define RX_PKT_V3_CMPL_HI_METADATA0_DE 0x1000UL
+ /* When meta_format=1, this value is the VLAN PRI. */
+ #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK 0xe000UL
+ #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_SFT 13
+ u32 timestamp;
+};
+
struct rx_prod_pkt_bd {
u16 flags_type;
#define RX_PROD_PKT_BD_TYPE_MASK 0x3fUL
@@ -705,6 +896,8 @@ struct rx_info {
u32 drop_err;
u32 drop_lb;
u32 drop_vlan;
+ u8 epoch;
+ u8 res[3];
};
#define VALID_DRIVER_REG 0x0001
@@ -750,7 +943,6 @@ struct bnxt {
struct nq_info nq; /* completion info. */
u16 nq_ring_id;
u8 queue_id;
- u8 thor;
u16 last_resp_code;
u16 seq_id;
u32 flag_hwrm;
@@ -792,6 +984,7 @@ struct bnxt {
u32 mba_cfg2;
u32 medium;
u16 support_speeds;
+ u16 auto_link_speeds2_mask;
u32 link_set;
u8 media_detect;
u8 rsvd;
@@ -868,4 +1061,8 @@ struct bnxt {
FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR | \
FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR)
-#define CHIP_NUM_57500 0x1750
+#define CHIP_NUM_57508 0x1750
+#define CHIP_NUM_57504 0x1751
+#define CHIP_NUM_57502 0x1752
+
+#define CHIP_NUM_57608 0x1760
diff --git a/src/drivers/net/bnxt/bnxt_dbg.h b/src/drivers/net/bnxt/bnxt_dbg.h
index 188978ad..14540281 100644
--- a/src/drivers/net/bnxt/bnxt_dbg.h
+++ b/src/drivers/net/bnxt/bnxt_dbg.h
@@ -475,7 +475,7 @@ void dbg_rx_stat(struct bnxt *bp)
#endif
#if defined(DEBUG_CQ)
-static void dump_cq(struct cmpl_base *cmp, u16 cid)
+static void dump_cq(struct cmpl_base *cmp, u16 cid, u8 toggle)
{
dbg_prn("- CQ Type ");
switch (cmp->type & CMPL_BASE_TYPE_MASK) {
@@ -495,7 +495,7 @@ static void dump_cq(struct cmpl_base *cmp, u16 cid)
dbg_prn("%04x", (u16)(cmp->type & CMPL_BASE_TYPE_MASK));
break;
}
- dbg_prn(" cid %d", cid);
+ dbg_prn(" cid %d, tog %d", cid, toggle);
#if defined(DEBUG_CQ_DUMP)
dump_mem((u8 *)cmp, (u32)sizeof(struct cmpl_base), DISP_U8);
#else
@@ -513,7 +513,7 @@ static void dump_nq(struct nq_base *nqp, u16 cid)
#endif
}
#else
-#define dump_cq(cq, id)
+#define dump_cq(cq, id, toggle)
#define dump_nq(nq, id)
#endif
diff --git a/src/drivers/net/bnxt/bnxt_hsi.h b/src/drivers/net/bnxt/bnxt_hsi.h
index 086acb8b..dbcffd90 100644
--- a/src/drivers/net/bnxt/bnxt_hsi.h
+++ b/src/drivers/net/bnxt/bnxt_hsi.h
@@ -2929,7 +2929,7 @@ struct hwrm_func_drv_if_change_output {
u8 valid;
};
-/* hwrm_port_phy_cfg_input (size:448b/56B) */
+/* hwrm_port_phy_cfg_input (size:512b/64B) */
struct hwrm_port_phy_cfg_input {
__le16 req_type;
__le16 cmpl_ring;
@@ -2952,6 +2952,15 @@ struct hwrm_port_phy_cfg_input {
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
+ #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
+
__le32 enables;
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
@@ -2964,6 +2973,10 @@ struct hwrm_port_phy_cfg_input {
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
+ #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
+ #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL
+ #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL
__le16 port_id;
__le16 force_link_speed;
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
@@ -3049,11 +3062,48 @@ struct hwrm_port_phy_cfg_input {
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
- u8 unused_2[2];
+ __le16 force_pam4_link_speed;
+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
+ #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
__le32 tx_lpi_timer;
#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
- __le32 unused_3;
+ __le16 auto_link_pam4_speed_mask;
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
+ __le16 force_link_speeds2;
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
+ #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
+ __le16 auto_link_speeds2_mask;
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL
+ #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL
+ u8 unused_2[6];
};
/* hwrm_port_phy_cfg_output (size:128b/16B) */
@@ -3087,7 +3137,7 @@ struct hwrm_port_phy_qcfg_input {
u8 unused_0[6];
};
-/* hwrm_port_phy_qcfg_output (size:768b/96B) */
+/* hwrm_port_phy_qcfg_output (size:832b/104B) */
struct hwrm_port_phy_qcfg_output {
__le16 error_code;
__le16 req_type;
@@ -3098,7 +3148,23 @@ struct hwrm_port_phy_qcfg_output {
#define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
#define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
- u8 unused_0;
+ u8 active_fec_signal_mode;
+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL
+ #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST HWRM_PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
+ #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
__le16 link_speed;
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
@@ -3111,6 +3177,7 @@ struct hwrm_port_phy_qcfg_output {
#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
+ #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
u8 duplex_cfg;
@@ -3249,7 +3316,31 @@ struct hwrm_port_phy_qcfg_output {
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
- #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL
+ #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4
u8 media_type;
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
@@ -3330,15 +3421,90 @@ struct hwrm_port_phy_qcfg_output {
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
+ #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
u8 duplex_state;
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
u8 option_flags;
#define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
+ #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL
+ #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL
char phy_vendor_name[16];
char phy_vendor_partnumber[16];
- u8 unused_2[7];
+ __le16 support_pam4_speeds;
+ #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
+ __le16 force_pam4_link_speed;
+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
+ #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
+ __le16 auto_pam4_link_speed_mask;
+ #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
+ #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
+ #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
+ u8 link_partner_pam4_adv_speeds;
+ #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
+ #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
+ #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
+ u8 link_down_reason;
+ #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
+ __le16 support_speeds2;
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL
+ #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL
+ __le16 force_link_speeds2;
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL
+ #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112
+ __le16 auto_link_speeds2;
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL
+ #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL
+ u8 active_lanes;
u8 valid;
};
@@ -3888,7 +4054,7 @@ struct hwrm_port_phy_qcaps_input {
u8 unused_0[6];
};
-/* hwrm_port_phy_qcaps_output (size:192b/24B) */
+/* hwrm_port_phy_qcaps_output (size:320b/40B) */
struct hwrm_port_phy_qcaps_output {
__le16 error_code;
__le16 req_type;
@@ -3954,6 +4120,53 @@ struct hwrm_port_phy_qcaps_output {
#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
#define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
#define PORT_PHY_QCAPS_RESP_VALID_SFT 24
+ __le16 supported_pam4_speeds_auto_mode;
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
+ __le16 supported_pam4_speeds_force_mode;
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
+ __le16 flags2;
+ #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL
+ #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL
+ #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL
+ #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL
+ u8 internal_port_cnt;
+ u8 unused_0;
+ __le16 supported_speeds2_force_mode;
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL
+ __le16 supported_speeds2_auto_mode;
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL
+ #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL
+ u8 unused_1[3];
+ u8 valid;
};
/* hwrm_port_phy_i2c_write_input (size:832b/104B) */
diff --git a/src/drivers/net/davicom.c b/src/drivers/net/davicom.c
index 9d3d8b91..0c96796d 100644
--- a/src/drivers/net/davicom.c
+++ b/src/drivers/net/davicom.c
@@ -689,9 +689,9 @@ static struct nic_operations davicom_operations = {
};
static struct pci_device_id davicom_nics[] = {
+PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0),
PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0),
-PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */
};
diff --git a/src/drivers/net/dmfe.c b/src/drivers/net/dmfe.c
index 2ea0d2b2..53b05815 100644
--- a/src/drivers/net/dmfe.c
+++ b/src/drivers/net/dmfe.c
@@ -1208,9 +1208,9 @@ static struct nic_operations dmfe_operations = {
};
static struct pci_device_id dmfe_nics[] = {
+ PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
- PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0), /* Needs probably some fixing */
};
diff --git a/src/drivers/net/eepro100.c b/src/drivers/net/eepro100.c
index a0551a89..49b00d44 100644
--- a/src/drivers/net/eepro100.c
+++ b/src/drivers/net/eepro100.c
@@ -1126,8 +1126,12 @@ PCI_ROM(0x8086, 0x103b, "82562etb", "Intel PRO100 VE 82562ETB", 0),
PCI_ROM(0x8086, 0x103c, "eepro100-103c", "Intel PRO/100 VM Network Connection", 0),
PCI_ROM(0x8086, 0x103d, "eepro100-103d", "Intel PRO/100 VE Network Connection", 0),
PCI_ROM(0x8086, 0x103e, "eepro100-103e", "Intel PRO/100 VM Network Connection", 0),
+PCI_ROM(0x8086, 0x1050, "82562ez", "Intel 82562EZ Network Connection", 0),
PCI_ROM(0x8086, 0x1051, "prove", "Intel PRO/100 VE Network Connection", 0),
PCI_ROM(0x8086, 0x1059, "82551qm", "Intel PRO/100 M Mobile Connection", 0),
+PCI_ROM(0x8086, 0x1065, "82562-3", "Intel 82562 based Fast Ethernet Connection", 0),
+PCI_ROM(0x8086, 0x1092, "82562-3", "Intel Pro/100 VE Network", 0),
+PCI_ROM(0x8086, 0x10fe, "82552", "Intel 82552 10/100 Network Connection", 0),
PCI_ROM(0x8086, 0x1209, "82559er", "Intel EtherExpressPro100 82559ER", 0),
PCI_ROM(0x8086, 0x1227, "82865", "Intel 82865 EtherExpress PRO/100A", 0),
PCI_ROM(0x8086, 0x1228, "82556", "Intel 82556 EtherExpress PRO/100 Smart", 0),
@@ -1135,13 +1139,9 @@ PCI_ROM(0x8086, 0x1229, "eepro100", "Intel EtherExpressPro100", 0),
PCI_ROM(0x8086, 0x2449, "82562em", "Intel EtherExpressPro100 82562EM", 0),
PCI_ROM(0x8086, 0x2459, "82562-1", "Intel 82562 based Fast Ethernet Connection", 0),
PCI_ROM(0x8086, 0x245d, "82562-2", "Intel 82562 based Fast Ethernet Connection", 0),
-PCI_ROM(0x8086, 0x1050, "82562ez", "Intel 82562EZ Network Connection", 0),
-PCI_ROM(0x8086, 0x1065, "82562-3", "Intel 82562 based Fast Ethernet Connection", 0),
+PCI_ROM(0x8086, 0x27dc, "eepro100-27dc", "Intel 82801G (ICH7) Chipset Ethernet Controller", 0),
PCI_ROM(0x8086, 0x5200, "eepro100-5200", "Intel EtherExpress PRO/100 Intelligent Server", 0),
PCI_ROM(0x8086, 0x5201, "eepro100-5201", "Intel EtherExpress PRO/100 Intelligent Server", 0),
-PCI_ROM(0x8086, 0x1092, "82562-3", "Intel Pro/100 VE Network", 0),
-PCI_ROM(0x8086, 0x27dc, "eepro100-27dc", "Intel 82801G (ICH7) Chipset Ethernet Controller", 0),
-PCI_ROM(0x8086, 0x10fe, "82552", "Intel 82552 10/100 Network Connection", 0),
};
/* Cards with device ids 0x1030 to 0x103F, 0x2449, 0x2459 or 0x245D might need
diff --git a/src/drivers/net/forcedeth.c b/src/drivers/net/forcedeth.c
index ec3a5bdb..b4019d04 100644
--- a/src/drivers/net/forcedeth.c
+++ b/src/drivers/net/forcedeth.c
@@ -1928,17 +1928,17 @@ forcedeth_remove ( struct pci_device *pdev )
}
static struct pci_device_id forcedeth_nics[] = {
- PCI_ROM(0x10DE, 0x01C3, "nForce", "nForce Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
+ PCI_ROM(0x10DE, 0x0037, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
+ PCI_ROM(0x10DE, 0x0038, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
+ PCI_ROM(0x10DE, 0x0056, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
+ PCI_ROM(0x10DE, 0x0057, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
PCI_ROM(0x10DE, 0x0066, "nForce2", "nForce2 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
- PCI_ROM(0x10DE, 0x00D6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
PCI_ROM(0x10DE, 0x0086, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
PCI_ROM(0x10DE, 0x008C, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
- PCI_ROM(0x10DE, 0x00E6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
+ PCI_ROM(0x10DE, 0x00D6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
PCI_ROM(0x10DE, 0x00DF, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
- PCI_ROM(0x10DE, 0x0056, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
- PCI_ROM(0x10DE, 0x0057, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
- PCI_ROM(0x10DE, 0x0037, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
- PCI_ROM(0x10DE, 0x0038, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
+ PCI_ROM(0x10DE, 0x00E6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
+ PCI_ROM(0x10DE, 0x01C3, "nForce", "nForce Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
PCI_ROM(0x10DE, 0x0268, "MCP51", "MCP51 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX),
PCI_ROM(0x10DE, 0x0269, "MCP51", "MCP51 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX),
PCI_ROM(0x10DE, 0x0372, "MCP55", "MCP55 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X| DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED| DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX),
@@ -1955,14 +1955,14 @@ static struct pci_device_id forcedeth_nics[] = {
PCI_ROM(0x10DE, 0x054D, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x054E, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x054F, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
- PCI_ROM(0x10DE, 0x07DC, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
- PCI_ROM(0x10DE, 0x07DD, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
- PCI_ROM(0x10DE, 0x07DE, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
- PCI_ROM(0x10DE, 0x07DF, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0760, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0761, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0762, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0763, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
+ PCI_ROM(0x10DE, 0x07DC, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
+ PCI_ROM(0x10DE, 0x07DD, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
+ PCI_ROM(0x10DE, 0x07DE, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
+ PCI_ROM(0x10DE, 0x07DF, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0AB0, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0AB1, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
PCI_ROM(0x10DE, 0x0AB2, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
diff --git a/src/drivers/net/intel.c b/src/drivers/net/intel.c
index 46527bdb..7879714f 100644
--- a/src/drivers/net/intel.c
+++ b/src/drivers/net/intel.c
@@ -1043,6 +1043,7 @@ static struct pci_device_id intel_nics[] = {
PCI_ROM ( 0x8086, 0x0d4f, "i219v-10", "I219-V (10)", INTEL_I219 ),
PCI_ROM ( 0x8086, 0x0d53, "i219lm-12", "I219-LM (12)", INTEL_I219 ),
PCI_ROM ( 0x8086, 0x0d55, "i219v-12", "I219-V (12)", INTEL_I219 ),
+ PCI_ROM ( 0x8086, 0x0dc5, "i219lm-23", "I219-LM (23)", INTEL_I219 ),
PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
diff --git a/src/drivers/net/iphone.c b/src/drivers/net/iphone.c
index 7d0eb4b6..bbac527b 100644
--- a/src/drivers/net/iphone.c
+++ b/src/drivers/net/iphone.c
@@ -1304,7 +1304,9 @@ ipair_tx ( struct ipair *ipair, const char *fmt, ... ) {
memset ( hdr, 0, sizeof ( *hdr ) );
hdr->len = htonl ( len );
msg = iob_put ( iobuf, len );
+ va_start ( args, fmt );
vsnprintf ( msg, len, fmt, args );
+ va_end ( args );
DBGC2 ( ipair, "IPAIR %p transmitting:\n%s\n", ipair, msg );
/* Transmit message */
diff --git a/src/drivers/net/marvell/aqc1xx.c b/src/drivers/net/marvell/aqc1xx.c
new file mode 100644
index 00000000..42b8164a
--- /dev/null
+++ b/src/drivers/net/marvell/aqc1xx.c
@@ -0,0 +1,643 @@
+/** @file
+ *
+ * Marvell AQtion family network card driver.
+ *
+ * Copyright(C) 2017-2021 Marvell
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+FILE_LICENCE ( BSD2 );
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <byteswap.h>
+#include <ipxe/netdevice.h>
+#include <ipxe/ethernet.h>
+#include <ipxe/if_ether.h>
+#include <ipxe/iobuf.h>
+#include <ipxe/malloc.h>
+#include <ipxe/pci.h>
+#include <ipxe/profile.h>
+
+#include "aqc1xx.h"
+
+extern struct atl_hw_ops atl_hw;
+extern struct atl_hw_ops atl2_hw;
+
+/** @file
+*
+* Marvell AQC network card driver
+*
+*/
+
+static int atl_ring_alloc ( const struct atl_nic *nic, struct atl_ring *ring,
+ uint32_t desc_size, uint32_t reg_base )
+{
+ physaddr_t phy_addr;
+
+ /* Allocate ring buffer.*/
+ ring->length = ATL_RING_SIZE * desc_size;
+ ring->ring = dma_alloc ( nic->dma, &ring->map, ring->length,
+ ring->length );
+
+ if ( !ring->ring )
+ return -ENOMEM;
+
+ /* Initialize the descriptor ring */
+ memset ( ring->ring, 0, ring->length );
+
+ /* Program ring address */
+ phy_addr = dma ( &ring->map, ring->ring );
+
+ /* Write ring address (hi & low parts).*/
+ ATL_WRITE_REG ( (uint32_t)phy_addr, reg_base );
+ ATL_WRITE_REG ( (uint32_t)(((uint64_t)phy_addr) >> 32), reg_base + 4 );
+
+ /* Write ring length.*/
+ ATL_WRITE_REG ( ATL_RING_SIZE, reg_base + 8 );
+
+ ring->sw_head = ring->sw_tail = 0;
+
+ DBGC ( nic, "AQUANTIA: %p ring is at [%08llx,%08llx), reg base %#x\n",
+ nic, ((unsigned long long)phy_addr),
+ ((unsigned long long) phy_addr + ring->length), reg_base );
+
+ return 0;
+}
+
+static void atl_ring_free ( struct atl_ring *ring )
+{
+ dma_free ( &ring->map, ring->ring, ring->length );
+ ring->ring = NULL;
+ ring->length = 0;
+}
+
+static void atl_ring_next_dx ( unsigned int *val )
+{
+ ++( *val );
+ if ( *val == ATL_RING_SIZE )
+ *val = 0;
+}
+
+int atl_ring_full ( const struct atl_ring *ring )
+{
+ unsigned int tail = ring->sw_tail;
+ atl_ring_next_dx ( &tail );
+ return tail == ring->sw_head;
+}
+
+void atl_rx_ring_fill ( struct atl_nic *nic )
+{
+ struct atl_desc_rx *rx;
+ struct io_buffer *iobuf;
+ physaddr_t address;
+ unsigned int refilled = 0;
+
+ /* Refill ring */
+ while ( !atl_ring_full ( &nic->rx_ring ) ) {
+
+ /* Allocate I/O buffer */
+ iobuf = alloc_rx_iob ( ATL_RX_MAX_LEN, nic->dma );
+ if ( !iobuf ) {
+ /* Wait for next refill */
+ break;
+ }
+
+ /* Get next receive descriptor */
+ rx = ( struct atl_desc_rx * )nic->rx_ring.ring +
+ nic->rx_ring.sw_tail;
+
+ /* Populate receive descriptor */
+ address = iob_dma ( iobuf );
+ rx->data_addr = address;
+ rx->hdr_addr = 0;
+
+ /* Record I/O buffer */
+ assert ( nic->iobufs[nic->rx_ring.sw_tail] == NULL );
+ nic->iobufs[nic->rx_ring.sw_tail] = iobuf;
+
+ DBGC( nic, "AQUANTIA: RX[%d] is [%llx,%llx)\n",
+ nic->rx_ring.sw_tail,
+ ( (unsigned long long)address),
+ ( (unsigned long long)address + ATL_RX_MAX_LEN) );
+
+ atl_ring_next_dx ( &nic->rx_ring.sw_tail );
+ refilled++;
+ }
+
+ /* Push descriptors to card, if applicable */
+ if ( refilled ) {
+ wmb();
+ ATL_WRITE_REG ( nic->rx_ring.sw_tail, ATL_RING_TAIL_PTR );
+ }
+}
+
+/**
+* Open network device
+*
+* @v netdev Network device
+* @ret rc Return status code
+*/
+static int atl_open ( struct net_device *netdev )
+{
+ struct atl_nic *nic = netdev->priv;
+ uint32_t ctrl = 0;
+
+ /* Tx ring */
+ if ( atl_ring_alloc ( nic, &nic->tx_ring, sizeof(struct atl_desc_tx),
+ ATL_TX_DMA_DESC_ADDR ) != 0 )
+ goto err_tx_alloc;
+
+ /* Rx ring */
+ if ( atl_ring_alloc ( nic, &nic->rx_ring, sizeof(struct atl_desc_rx),
+ ATL_RX_DMA_DESC_ADDR ) != 0 )
+ goto err_rx_alloc;
+
+ /* Allocate interrupt vectors */
+ ATL_WRITE_REG ( (ATL_IRQ_CTRL_COR_EN | ATL_IRQ_CTRL_REG_RST_DIS),
+ ATL_IRQ_CTRL );
+
+ /*TX & RX Interruprt Mapping*/
+ ctrl = ATL_IRQ_MAP_REG1_RX0 | ATL_IRQ_MAP_REG1_RX0_EN |
+ ATL_IRQ_MAP_REG1_TX0 | ATL_IRQ_MAP_REG1_TX0_EN;
+ ATL_WRITE_REG ( ctrl, ATL_IRQ_MAP_REG1 );
+
+ /*TX interrupt ctrl reg*/
+ ATL_WRITE_REG ( ATL_TX_IRQ_CTRL_WB_EN, ATL_TX_IRQ_CTRL );
+
+ /*RX interrupt ctrl reg*/
+ ATL_WRITE_REG ( ATL_RX_IRQ_CTRL_WB_EN, ATL_RX_IRQ_CTRL );
+
+ /*RX data path*/
+ ctrl = ATL_IRQ_TX | ATL_IRQ_RX;
+ /* itr mask */
+ ATL_WRITE_REG ( ctrl, ATL_ITR_MSKS );
+ ATL_WRITE_REG ( (uint32_t)ATL_RX_MAX_LEN / 1024U,
+ ATL_RX_DMA_DESC_BUF_SIZE );
+
+ /*filter global ctrl */
+ ctrl = ATL_RPF_CTRL1_BRC_EN | ATL_RPF_CTRL1_L2_PROMISC |
+ ATL_RPF_CTRL1_ACTION | ATL_RPF_CTRL1_BRC_TSH;
+ ATL_WRITE_REG ( ctrl, ATL_RPF_CTRL1 );
+
+ /* vlan promisc */
+ ATL_WRITE_REG ( ATL_RPF_CTRL2_VLAN_PROMISC, ATL_RPF_CTRL2 );
+ /* enable rpf2 */
+ ATL_WRITE_REG ( ATL_RPF2_CTRL_EN, ATL_RPF2_CTRL );
+
+ /* RX Packet Buffer 0 Register 1 */
+ ATL_WRITE_REG ( ATL_RPB0_CTRL1_SIZE, ATL_RPB0_CTRL1 );
+
+ /*RX Packet Buffer 0 Register 2 */
+ ctrl = ATL_RPB0_CTRL2_LOW_TSH | ATL_RPB0_CTRL2_HIGH_TSH |
+ ATL_RPB0_CTRL2_FC_EN;
+ ATL_WRITE_REG ( ctrl, ATL_RPB0_CTRL2 );
+
+ /*RPB global ctrl*/
+ ctrl = ATL_READ_REG(ATL_RPB_CTRL);
+ ctrl |= (ATL_RPB_CTRL_EN | ATL_RPB_CTRL_FC);
+ ATL_WRITE_REG ( ctrl, ATL_RPB_CTRL );
+
+ /*TX data path*/
+ /* enable tpo2 */
+ ATL_WRITE_REG ( ATL_TPO2_EN, ATL_TPO2_CTRL );
+ /* tpb global ctrl *** */
+ ATL_WRITE_REG ( ATL_TPB0_CTRL1_SIZE, ATL_TPB0_CTRL1 );
+
+ ctrl = ATL_TPB0_CTRL2_LOW_TSH | ATL_TPB0_CTRL2_HIGH_TSH;
+ /* tpb global ctrl *** */
+ ATL_WRITE_REG ( ctrl, ATL_TPB0_CTRL2 );
+
+ ctrl = ATL_READ_REG ( ATL_TPB_CTRL );
+ ctrl |= ( ATL_TPB_CTRL_EN | ATL_TPB_CTRL_PAD_EN );
+ /* tpb global ctrl */
+ ATL_WRITE_REG ( ctrl, ATL_TPB_CTRL );
+
+ /*Enable rings*/
+ ATL_WRITE_REG ( ATL_READ_REG ( ATL_RING_TX_CTRL ) | ATL_RING_TX_CTRL_EN,
+ ATL_RING_TX_CTRL );
+ ATL_WRITE_REG ( ATL_READ_REG ( ATL_RING_RX_CTRL ) | ATL_RING_RX_CTRL_EN,
+ ATL_RING_RX_CTRL );
+
+ if ( nic->flags == ATL_FLAG_A2 ) {
+ ATL_WRITE_REG ( ATL2_RPF_NEW_EN_ADR_EN, ATL2_RPF_NEW_EN_ADR );
+ }
+
+ atl_rx_ring_fill ( nic );
+
+ nic->hw_ops->start ( nic );
+
+ return 0;
+
+err_rx_alloc:
+ atl_ring_free ( &nic->tx_ring );
+
+err_tx_alloc:
+ return -ENOMEM;
+}
+
+/**
+* Close network device
+*
+* @v netdev Network device
+*/
+static void atl_close ( struct net_device *netdev )
+{
+ struct atl_nic *nic = netdev->priv;
+
+ nic->hw_ops->stop ( nic );
+ /* rpb global ctrl */
+ ATL_WRITE_REG ( ATL_RPB_CTRL_DIS, ATL_RPB_CTRL );
+ /* tgb global ctrl */
+ ATL_WRITE_REG ( ATL_TPB_CTRL_DIS, ATL_TPB_CTRL);
+
+ ATL_WRITE_REG ( ATL_READ_REG(ATL_RING_TX_CTRL) | (~ATL_RING_TX_CTRL_EN),
+ ATL_RING_TX_CTRL );
+ ATL_WRITE_REG ( ATL_READ_REG(ATL_RING_RX_CTRL) | (~ATL_RING_RX_CTRL_EN),
+ ATL_RING_RX_CTRL );
+
+ /* clear itr mask */
+ ATL_WRITE_REG ( ATL_ITR_MSKS_DIS, ATL_ITR_MSKS );
+
+ /* Reset the NIC */
+ nic->hw_ops->reset ( nic );
+
+ atl_ring_free ( &nic->tx_ring );
+ atl_ring_free ( &nic->rx_ring );
+}
+
+/**
+* Transmit packet
+*
+* @v netdev Network device
+* @v iobuf I/O buffer
+* @ret rc Return status code
+*/
+int atl_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
+{
+ struct atl_nic *nic = netdev->priv;
+ struct atl_desc_tx *tx;
+ physaddr_t address;
+ uint32_t len;
+
+ /* Get next transmit descriptor */
+ if ( atl_ring_full ( &nic->tx_ring ) ) {
+ DBGC ( nic, "AQUANTIA: %p out of transmit descriptors\n", nic );
+ return -ENOBUFS;
+ }
+
+ tx = (struct atl_desc_tx *)nic->tx_ring.ring + nic->tx_ring.sw_tail;
+
+ /* Populate transmit descriptor */
+ memset ( tx, 0, sizeof ( *tx ) );
+ address = iob_dma ( iobuf );
+ tx->address = address;
+ len = iob_len ( iobuf );
+
+ tx->status = 0x1;
+ tx->status = ( (tx->status) & ~ATL_DESC_TX_BUF_LEN_MASK) |
+ ((len << ATL_DESC_TX_BUF_LEN_OFFSET) &
+ ATL_DESC_TX_BUF_LEN_MASK );
+ tx->status = ((tx->status) & ~ATL_DESC_TX_EOP_MASK) |
+ ( (ATL_DESC_TX_DX_EOP_VALUE << ATL_DESC_TX_EOP_OFFSET) &
+ ATL_DESC_TX_EOP_MASK );
+ tx->status = ( (tx->status) & ~ATL_DESC_TX_CMD_MASK) |
+ ((ATL_DESC_TX_CMD_VALUE << ATL_DESC_TX_CMD_OFFSET) &
+ ATL_DESC_TX_CMD_MASK );
+ tx->flag = ( (tx->flag) & ~ATL_DESC_TX_PAY_LEN_MASK) |
+ ((len << ATL_DESC_TX_PAY_LEN_OFFSET) &
+ ATL_DESC_TX_PAY_LEN_MASK );
+ wmb();
+
+ DBGC2 ( nic, "AQUANTIA: %p TX[%d] is [%llx, %llx]\n",
+ nic, nic->tx_ring.sw_tail,
+ ( ( unsigned long long ) address ),
+ ( ( unsigned long long ) address + len ) );
+
+ atl_ring_next_dx ( &nic->tx_ring.sw_tail );
+ ATL_WRITE_REG ( nic->tx_ring.sw_tail, ATL_RING_TAIL );
+
+ return 0;
+}
+
+void atl_check_link ( struct net_device *netdev )
+{
+ struct atl_nic *nic = netdev->priv;
+ uint32_t link_state;
+
+ /* Read link status */
+ link_state = nic->hw_ops->get_link ( nic );
+
+ DBGC ( nic, "AQUANTIA: %p link status is %08x\n", nic, link_state );
+
+ if ( link_state != nic->link_state ) {
+ if ( link_state ) {
+ DBGC ( nic, "AQUANTIA: link up\n");
+ netdev_link_up ( netdev );
+ } else {
+ DBGC ( nic, "AQUANTIA: link lost\n");
+ netdev_link_down ( netdev );
+ }
+ nic->link_state = link_state;
+ }
+}
+
+/**
+* Poll for completed packets
+*
+* @v netdev Network device
+*/
+void atl_poll_tx ( struct net_device *netdev )
+{
+ struct atl_nic *nic = netdev->priv;
+ struct atl_desc_tx_wb *tx;
+
+ /* Check for completed packets */
+ while ( nic->tx_ring.sw_head != nic->tx_ring.sw_tail ) {
+
+ /* Get next transmit descriptor */
+ tx = ( struct atl_desc_tx_wb * )nic->tx_ring.ring +
+ nic->tx_ring.sw_head;
+
+ /* Stop if descriptor is still in use */
+ if ( !(tx->status & cpu_to_le32 ( ATL_TX_DESC_STATUS_DD ) ) )
+ return;
+
+ DBGC2 ( nic, "AQUANTIA: %p TX[%d] complete\n",
+ nic, nic->tx_ring.sw_head );
+
+ /* Complete TX descriptor */
+ atl_ring_next_dx ( &nic->tx_ring.sw_head );
+ netdev_tx_complete_next ( netdev );
+ }
+}
+
+/**
+* Poll for received packets
+*
+* @v netdev Network device
+*/
+void atl_poll_rx ( struct net_device *netdev )
+{
+ struct atl_nic *nic = netdev->priv;
+ struct atl_desc_rx_wb *rx;
+ struct io_buffer *iobuf;
+ size_t len;
+
+ /* Check for received packets */
+ while ( nic->rx_ring.sw_head != nic->rx_ring.sw_tail ) {
+
+ /* Get next receive descriptor */
+ rx = (struct atl_desc_rx_wb *)nic->rx_ring.ring +
+ nic->rx_ring.sw_head;
+
+ /* Stop if descriptor is still in use */
+ if ( !(rx->status & cpu_to_le16(ATL_RX_DESC_STATUS_DD)) )
+ return;
+
+ /* Populate I/O buffer */
+ iobuf = nic->iobufs[nic->rx_ring.sw_head];
+ nic->iobufs[nic->rx_ring.sw_head] = NULL;
+ len = le16_to_cpu ( rx->pkt_len );
+ iob_put ( iobuf, len );
+
+ /* Hand off to network stack */
+ DBGC ( nic, "AQUANTIA: %p RX[%d] complete (length %zd)\n",
+ nic, nic->rx_ring.sw_head, len );
+
+ netdev_rx ( netdev, iobuf );
+
+ atl_ring_next_dx ( &nic->rx_ring.sw_head );
+ }
+}
+
+/**
+* Poll for completed and received packets
+*
+* @v netdev Network device
+*/
+static void atl_poll ( struct net_device *netdev )
+{
+ struct atl_nic *nic = netdev->priv;
+
+ /* Check link state */
+ atl_check_link ( netdev );
+
+ /* Poll for TX completions */
+ atl_poll_tx ( netdev );
+
+ /* Poll for RX completions */
+ atl_poll_rx ( netdev );
+
+ /* Refill RX ring */
+ atl_rx_ring_fill ( nic );
+}
+
+/**
+* Enable or disable interrupts
+*
+* @v netdev Network device
+* @v enable Interrupts should be enabled
+*/
+static void atl_irq ( struct net_device *netdev, int enable )
+{
+ struct atl_nic *nic = netdev->priv;
+ uint32_t mask;
+
+ mask = ( ATL_IRQ_TX | ATL_IRQ_RX );
+ if ( enable )
+ ATL_WRITE_REG ( mask, ATL_ITR_MSKS );
+ else
+ ATL_WRITE_REG ( mask, ATL_ITR_MSKC );
+}
+
+/** Marvell network device operations */
+static struct net_device_operations atl_operations = {
+ .open = atl_open,
+ .close = atl_close,
+ .transmit = atl_transmit,
+ .poll = atl_poll,
+ .irq = atl_irq,
+};
+
+/******************************************************************************
+*
+* PCI interface
+*
+*******************************************************************************
+*/
+
+/**
+* Probe PCI device
+*
+* @v pci PCI device
+* @ret rc Return status code
+*/
+static int atl_probe ( struct pci_device *pci )
+{
+ struct net_device *netdev;
+ struct atl_nic *nic;
+ int rc = ENOERR;
+ uint32_t io_size = 0;
+
+ /* Allocate and initialise net device */
+ netdev = alloc_etherdev ( sizeof( *nic ) );
+ if ( !netdev ) {
+ rc = -ENOMEM;
+ goto err_alloc;
+ }
+ netdev_init ( netdev, &atl_operations );
+ nic = netdev->priv;
+ pci_set_drvdata ( pci, netdev );
+ netdev->dev = &pci->dev;
+ memset( nic, 0, sizeof( *nic ) );
+ nic->flags = pci->id->driver_data;
+
+ /* Fix up PCI device */
+ adjust_pci_device ( pci );
+
+ switch ( nic->flags ) {
+ case ATL_FLAG_A1:
+ nic->hw_ops = &atl_hw;
+ io_size = ATL_BAR_SIZE;
+ break;
+ case ATL_FLAG_A2:
+ nic->hw_ops = &atl2_hw;
+ io_size = ATL2_BAR_SIZE;
+ break;
+ default:
+ goto err_unsupported;
+ break;
+ }
+
+ /* Map registers */
+ nic->regs = pci_ioremap ( pci, pci->membase, io_size );
+ if ( !nic->regs ) {
+ rc = -ENODEV;
+ goto err_ioremap;
+ }
+
+ /* Configure DMA */
+ nic->dma = &pci->dma;
+
+ /* Reset the NIC */
+ if ( ( rc = nic->hw_ops->reset ( nic ) ) != 0 )
+ goto err_reset;
+
+ /* Get MAC Address */
+ if ( ( rc = nic->hw_ops->get_mac ( nic, netdev->hw_addr ) ) != 0 )
+ goto err_mac;
+
+ /* Register network device */
+ if ( ( rc = register_netdev ( netdev ) ) != 0 )
+ goto err_register_netdev;
+
+ /* Set initial link state */
+ netdev_link_down ( netdev );
+
+ return 0;
+
+err_register_netdev:
+err_mac:
+ nic->hw_ops->reset ( nic );
+err_reset:
+ iounmap ( nic->regs );
+err_ioremap:
+ netdev_nullify ( netdev );
+ netdev_put ( netdev );
+err_unsupported:
+err_alloc:
+ return rc;
+}
+
+/**
+* Remove PCI device
+*
+* @v pci PCI device
+*/
+static void atl_remove ( struct pci_device *pci )
+{
+ struct net_device *netdev = pci_get_drvdata ( pci );
+ struct atl_nic *nic = netdev->priv;
+
+ /* Unregister network device */
+ unregister_netdev ( netdev );
+
+ /* Reset the NIC */
+ nic->hw_ops->reset ( nic );
+
+ /* Free network device */
+ iounmap ( nic->regs );
+ netdev_nullify ( netdev );
+ netdev_put ( netdev );
+}
+
+/** Marvell PCI device IDs */
+static struct pci_device_id atl_nics[] = {
+ /* Atlantic 1 */
+ /* 10G */
+ PCI_ROM(0x1D6A, 0x0001, "AQC07", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0xD107, "AQC07", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x07B1, "AQC07", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x87B1, "AQC07", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A1),
+
+ /* SFP */
+ PCI_ROM(0x1D6A, 0xD100, "AQC00", "Felicity Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x00B1, "AQC00", "Felicity Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x80B1, "AQC00", "Felicity Network Adapter", ATL_FLAG_A1),
+
+ /* 5G */
+ PCI_ROM(0x1D6A, 0xD108, "AQC08", "Marvell AQtion 5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x08B1, "AQC08", "Marvell AQtion 5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x88B1, "AQC08", "Marvell AQtion 5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x11B1, "AQC11", "Marvell AQtion 5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x91B1, "AQC11", "Marvell AQtion 5Gbit Network Adapter", ATL_FLAG_A1),
+
+ /* 2.5G */
+ PCI_ROM(0x1D6A, 0xD109, "AQC09", "Marvell AQtion 2.5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x09B1, "AQC09", "Marvell AQtion 2.5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x89B1, "AQC09", "Marvell AQtion 2.5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x12B1, "AQC12", "Marvell AQtion 2.5Gbit Network Adapter", ATL_FLAG_A1),
+ PCI_ROM(0x1D6A, 0x92B1, "AQC12", "Marvell AQtion 2.5Gbit Network Adapter", ATL_FLAG_A1),
+
+ /* Atlantic 2 */
+ PCI_ROM(0x1D6A, 0x00C0, "AQC13", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A2),
+ PCI_ROM(0x1D6A, 0x94C0, "AQC13", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A2),
+ PCI_ROM(0x1D6A, 0x93C0, "AQC13", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A2),
+ PCI_ROM(0x1D6A, 0x04C0, "AQC13", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A2),
+ PCI_ROM(0x1D6A, 0x14C0, "AQC13", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A2),
+ PCI_ROM(0x1D6A, 0x12C0, "AQC13", "Marvell AQtion 10Gbit Network Adapter", ATL_FLAG_A2),
+};
+
+/** Marvell PCI driver */
+struct pci_driver atl_driver __pci_driver = {
+ .ids = atl_nics,
+ .id_count = (sizeof(atl_nics) / sizeof(atl_nics[0])),
+ .probe = atl_probe,
+ .remove = atl_remove,
+}; \ No newline at end of file
diff --git a/src/drivers/net/marvell/aqc1xx.h b/src/drivers/net/marvell/aqc1xx.h
new file mode 100644
index 00000000..c3e34e1e
--- /dev/null
+++ b/src/drivers/net/marvell/aqc1xx.h
@@ -0,0 +1,270 @@
+/** @file
+ *
+ * Marvell AQtion family network card driver definitions.
+ *
+ * Copyright(C) 2017-2021 Marvell
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _ATLANTIC_H
+#define _ATLANTIC_H
+
+FILE_LICENCE ( BSD2 );
+
+#include <stdint.h>
+#include <ipxe/if_ether.h>
+#include <ipxe/nvs.h>
+
+#define ATL_BAR_SIZE 0x10000
+#define ATL2_BAR_SIZE 0x40000
+#define ATL_RING_SIZE 64
+#define ATL_RING_ALIGN 128
+#define ATL_RX_MAX_LEN 2048
+
+#define ATL_IRQ_TX 0x00000001U
+#define ATL_IRQ_RX 0x00000002U
+
+/*IRQ Status Register*/
+#define ATL_IRQ_STAT_REG 0x00002000U
+
+/* Interrupt Vector Allocation Register */
+#define ATL_IRQ_CTRL 0x00002300U
+#define ATL_IRQ_CTRL_COR_EN 0x00000080U /*IRQ clear on read */
+#define ATL_IRQ_CTRL_REG_RST_DIS 0x20000000U /*Register reset disable */
+
+/*TX/RX Interruprt Mapping*/
+#define ATL_IRQ_MAP_REG1 0x00002100U /*IRQ mapping register */
+
+#define ATL_IRQ_MAP_REG1_RX0_EN 0x00008000U /*IRQ RX0 enable*/
+#define ATL_IRQ_MAP_REG1_RX0 0x00000100U /*IRQ RX0*/
+
+#define ATL_IRQ_MAP_REG1_TX0_EN 0x80000000U /*IRQ TX0 enable*/
+#define ATL_IRQ_MAP_REG1_TX0 0x00000000U /*IRQ TX0*/
+
+/*TX interrupt ctrl reg*/
+#define ATL_TX_IRQ_CTRL 0x00007B40U
+#define ATL_TX_IRQ_CTRL_WB_EN 0x00000002U
+
+/*RX interrupt ctrl reg*/
+#define ATL_RX_IRQ_CTRL 0x00005A30U
+#define ATL_RX_IRQ_CTRL_WB_EN 0x00000004U
+
+#define ATL_GLB_CTRL 0x00000000U
+
+#define ATL_PCI_CTRL 0x00001000U
+#define ATL_PCI_CTRL_RST_DIS 0x20000000U
+
+#define ATL_RX_CTRL 0x00005000U
+#define ATL_RX_CTRL_RST_DIS 0x20000000U /*RPB reset disable */
+#define ATL_TX_CTRL 0x00007000U
+#define ATL_TX_CTRL_RST_DIS 0x20000000U /*TPB reset disable */
+
+/*RX data path control registers*/
+#define ATL_RPF2_CTRL 0x00005040U
+#define ATL_RPF2_CTRL_EN 0x000F0000U /* RPF2 enable*/
+#define ATL2_RPF_NEW_EN_ADR_EN 0x00000001U /*enable*/
+#define ATL2_RPF_NEW_EN_ADR 0x5104
+
+#define ATL_RPF_CTRL1 0x00005100U
+#define ATL_RPF_CTRL1_BRC_EN 0x00000001U /*Allow broadcast receive*/
+#define ATL_RPF_CTRL1_L2_PROMISC 0x00000008U /*L2 promiscious*/
+#define ATL_RPF_CTRL1_ACTION 0x00001000U /*Action to host*/
+#define ATL_RPF_CTRL1_BRC_TSH 0x00010000U /*Brc threshold 256 units per sec*/
+
+#define ATL_RPF_CTRL2 0x00005280U
+#define ATL_RPF_CTRL2_VLAN_PROMISC 0x00000002U /*VLAN promisc*/
+
+#define ATL_RPB_CTRL_DIS 0x0
+#define ATL_RPB_CTRL 0x00005700U
+#define ATL_RPB_CTRL_EN 0x00000001U /*RPB Enable*/
+#define ATL_RPB_CTRL_FC 0x00000010U /*RPB Enable*/
+#define ATL_RPB_CTRL_TC_MODE 0x00000100U /*RPB Traffic Class Mode*/
+
+#define ATL_RPB0_CTRL1 0x00005710U
+#define ATL_RPB0_CTRL1_SIZE 0x00000140U /*RPB size (in unit 1KB) \*/
+
+#define ATL_RPB0_CTRL2 0x00005714U
+
+/*Buffer Low Threshold (70% of RPB size in unit 32B)*/
+#define ATL_RPB0_CTRL2_LOW_TSH 0x00000C00U
+/*Buffer High Threshold(30% of RPB size in unit 32B)*/
+#define ATL_RPB0_CTRL2_HIGH_TSH 0x1C000000U
+#define ATL_RPB0_CTRL2_FC_EN 0x80000000U /*Flow control Enable*/
+
+#define ATL_RX_DMA_DESC_BUF_SIZE 0x00005b18U
+#define ATL_RX_DMA_DESC_ADDR 0x00005b00U
+
+/*TX data path control registers*/
+#define ATL_TPO2_CTRL 0x00007040U
+#define ATL_TPO2_EN 0x00010000U /*TPO2 Enable*/
+
+#define ATL_TPB_CTRL_DIS 0x0
+#define ATL_TPB_CTRL 0x00007900U
+#define ATL_TPB_CTRL_EN 0x00000001U /*TPB enable*/
+#define ATL_TPB_CTRL_PAD_EN 0x00000004U /*Tx pad insert enable*/
+#define ATL_TPB_CTRL_TC_MODE 0x00000100U /*Tx traffic Class Mode*/
+
+#define ATL_TPB0_CTRL1 0x00007910U
+#define ATL_TPB0_CTRL1_SIZE 0x000000A0U /*TPB Size (in unit 1KB)*/
+
+#define ATL_TPB0_CTRL2 0x00007914U
+/*Buffer Low Threshold(30% of RPB size in unit 32B)*/
+#define ATL_TPB0_CTRL2_LOW_TSH 0x00000600U
+/*Buffer High Threshold(30% of RPB size in unit 32B)*/
+#define ATL_TPB0_CTRL2_HIGH_TSH 0x0E000000U
+
+#define ATL_TX_DMA_DESC_ADDR 0x00007c00U
+
+/*Rings control registers*/
+#define ATL_RING_TX_CTRL 0x00007c08U
+#define ATL_RING_TX_CTRL_EN 0x80000000U /*Tx descriptor Enable*/
+
+#define ATL_RING_RX_CTRL 0x00005b08U
+#define ATL_RING_RX_CTRL_EN 0x80000000U /*Rx descriptor Enable*/
+
+#define ATL_RING_TAIL 0x00007c10U
+#define ATL_RING_TAIL_PTR 0x00005b10U
+
+/*IRQ control registers*/
+#define ATL_ITR_MSKS_DIS 0x0
+#define ATL_ITR_MSKS 0x00002060U
+#define ATL_ITR_MSKS_LSW 0x0000000CU
+#define ATL_ITR_MSKC 0x00002070U
+#define ATL_ITR_MSKC_LSW 0x0000000CU
+
+/*Link advertising*/
+#define ATL_LINK_ADV 0x00000368U
+#define ATL_SHUT_LINK 0x0
+#define ATL_LINK_ADV_AUTONEG 0xF20U
+
+#define ATL_LINK_ST 0x00000370U
+
+/*Semaphores*/
+#define ATL_SEM_RAM 0x000003a8U
+#define ATL_SEM_RAM_RESET 0X1
+
+/*Mailbox*/
+#define ATL_MBOX_ADDR 0x00000360U
+#define ATL_MBOX_CTRL1 0x00000200U
+#define ATL_MBOX_CTRL1_START_MBOX_OPT 0x8000
+
+#define ATL_MBOX_CTRL3 0x00000208U
+#define ATL_MBOX_CTRL5 0x0000020cU
+
+#define ATL_FLAG_A1 0x1
+#define ATL_FLAG_A2 0x2
+
+/*write register*/
+#define ATL_WRITE_REG(VAL, REG) writel(VAL, nic->regs + (REG))
+#define ATL_READ_REG(REG) readl(nic->regs + (REG)) /*read register*/
+
+struct atl_desc_tx {
+ uint64_t address;
+ uint32_t status;
+ uint32_t flag;
+} __attribute__((packed));
+
+#define ATL_DESC_TX_DX_TYPE_VALUE 0x1
+
+#define ATL_DESC_TX_DX_EOP_VALUE 0x1
+#define ATL_DESC_TX_EOP_MASK 0x00200000
+#define ATL_DESC_TX_EOP_OFFSET 21
+
+#define ATL_DESC_TX_CMD_MASK 0x3FC00000UL
+#define ATL_DESC_TX_CMD_OFFSET 22
+#define ATL_DESC_TX_CMD_VALUE 0x22
+
+#define ATL_DESC_TX_BUF_LEN_MASK 0x000FFFF0
+#define ATL_DESC_TX_BUF_LEN_OFFSET 5
+
+#define ATL_DESC_TX_PAY_LEN_MASK 0xFFFFC000
+#define ATL_DESC_TX_PAY_LEN_OFFSET 14
+
+struct atl_desc_tx_wb {
+ uint64_t rsvd1;
+ uint32_t status;
+ uint32_t rsvd4;
+} __attribute__((packed));
+
+#define ATL_TX_DESC_STATUS_DD 0x00100000UL
+
+struct atl_desc_rx {
+ uint64_t data_addr;
+ uint64_t hdr_addr;
+
+} __attribute__((packed));
+
+struct atl_desc_rx_wb {
+ uint64_t rsvd2;
+ uint16_t status;
+ uint16_t pkt_len;
+ uint32_t rsvd4;
+} __attribute__((packed));
+
+#define ATL_RX_DESC_STATUS_DD 0x0001UL
+#define ATL_RX_DESC_STATUS_EOP 0x0002UL
+struct atl_ring {
+ unsigned int sw_tail;
+ unsigned int sw_head;
+ void *ring;
+ /** Descriptor ring DMA mapping */
+ struct dma_mapping map;
+ unsigned int length;
+};
+
+struct atl_nic;
+
+struct atl_hw_ops {
+ int (*reset) (struct atl_nic *nic);
+ int (*start) (struct atl_nic *nic);
+ int (*stop) (struct atl_nic *nic);
+ int (*get_link) (struct atl_nic *nic);
+ int (*get_mac) (struct atl_nic *, uint8_t *mac);
+};
+
+/** An aQuanita network card */
+struct atl_nic {
+ /** Registers */
+ void *regs;
+ /** Port number (for multi-port devices) */
+ unsigned int port;
+ /** DMA device */
+ struct dma_device *dma;
+ /** Flags */
+ unsigned int flags;
+ struct atl_ring tx_ring;
+ struct atl_ring rx_ring;
+ struct io_buffer *iobufs[ATL_RING_SIZE];
+ uint32_t link_state;
+ uint32_t mbox_addr;
+ struct atl_hw_ops *hw_ops;
+};
+
+struct atl_hw_stats {
+ uint32_t version;
+ uint32_t tid;
+};
+
+#endif /* _AQUANTIA_H */
diff --git a/src/drivers/net/marvell/atl2_hw.c b/src/drivers/net/marvell/atl2_hw.c
new file mode 100644
index 00000000..0c57a12f
--- /dev/null
+++ b/src/drivers/net/marvell/atl2_hw.c
@@ -0,0 +1,235 @@
+/** @file
+ *
+ * Marvell AQtion family network card driver, hardware-specific functions.
+ *
+ * Copyright(C) 2017-2021 Marvell
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+FILE_LICENCE ( BSD2 );
+
+#include <errno.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <byteswap.h>
+#include <ipxe/pci.h>
+#include "aqc1xx.h"
+#include "atl2_hw.h"
+
+static int atl2_hw_boot_completed_ ( struct atl_nic *nic )
+{
+ uint32_t reset_status = ATL_READ_REG ( ATL2_GLB_RST_CTRL2 );
+
+ return ( reset_status & ATL2_RESET_STATUS_BOOT_COMPLETED_MASK ) ||
+ ( ATL_READ_REG ( ATL2_HOST_ITR_REQ )
+ & ATL2_FW_HOST_INTERRUPT_REQUEST_READY );
+}
+
+void atl2_hw_read_shared_in_ ( struct atl_nic *nic, uint32_t offset,
+ uint32_t *data, uint32_t len )
+{
+ uint32_t i;
+
+ for (i = 0; i < len; ++i )
+ {
+ data[i] = ATL_READ_REG ( ATL2_MIF_SHARED_BUF_IN + offset + i * 4 );
+ }
+}
+
+void atl2_hw_write_shared_in_ ( struct atl_nic *nic, uint32_t offset,
+ uint32_t *data, uint32_t len )
+{
+ uint32_t i;
+
+ for ( i = 0; i < len; ++i )
+ {
+ ATL_WRITE_REG ( data[i], ATL2_MIF_SHARED_BUF_IN + offset + i * 4 );
+ }
+}
+
+int atl2_hw_finish_ack_ ( struct atl_nic *nic, uint32_t ms )
+{
+ uint32_t i;
+ int err = 0;
+
+ ATL_WRITE_REG ( ATL_READ_REG(ATL2_HOST_FINISHED_WRITE )
+ | 1, ATL2_HOST_FINISHED_WRITE );
+
+ for ( i = 0; i < (ms / 100); ++i )
+ {
+ if ( ( ATL_READ_REG(ATL2_MCP_BUSY_WRITE ) & 1 ) == 0 )
+ {
+ break;
+ }
+ udelay ( ATL2_DELAY_100 );
+ }
+ if (i == ( ms / 100 ) )
+ err = -ETIME;
+
+ return err;
+}
+
+int atl2_hw_fw_init_ ( struct atl_nic *nic )
+{
+ uint32_t val;
+ int err = 0;
+
+ atl2_hw_read_shared_in_ ( nic, ATL2_LINK_CTRL_IN_OFF, &val, 1 );
+ val |= ( ATL2_HOST_MODE_ACTIVE | ( 1U << 13 ) );
+ atl2_hw_write_shared_in_ ( nic, ATL2_LINK_CTRL_IN_OFF, &val, 1 );
+
+ atl2_hw_read_shared_in_ ( nic, ATL2_MTU_IN_OFF, &val, 1 );
+ val = 16352;
+ atl2_hw_write_shared_in_ ( nic, ATL2_MTU_IN_OFF, &val, 1 );
+
+ atl2_hw_read_shared_in_ ( nic, ATL2_LINK_OPTS_IN_OFF, &val, 1 );
+ val = 0;
+ atl2_hw_write_shared_in_( nic, ATL2_LINK_OPTS_IN_OFF, &val, 1 );
+ err = atl2_hw_finish_ack_ ( nic, 50000000 );
+
+ return err;
+}
+
+int atl2_hw_reset ( struct atl_nic *nic )
+{
+ int completed = 0;
+ uint32_t status = 0;
+ uint32_t request;
+ int err = 0;
+ int i;
+
+ request = ATL2_RESET_STATUS_REQ_GSR;
+
+ ATL_WRITE_REG ( request, ATL2_GLB_RST_CTRL2 );
+
+ /* Wait for boot code started every 10us, 200 ms */
+ for ( i = 0; i < 20000; ++i )
+ {
+ status = ATL_READ_REG ( ATL2_GLB_RST_CTRL2 );
+
+ if ( ( ( status & ATL2_RESET_STATUS_BC_STARTED ) &&
+ (status != 0xFFFFFFFFu ) ) )
+ break;
+
+ udelay ( ATL2_DELAY_10 );
+ }
+ if ( i == 20000 )
+ {
+ DBGC ( nic, "Boot code hanged" );
+ err = -EIO;
+ goto err_exit;
+ }
+
+ /* Wait for boot succeed, failed or host request every 10us, 480ms */
+ for ( i = 0; i < 48000; ++i )
+ {
+ completed = atl2_hw_boot_completed_ ( nic );
+ if ( completed )
+ break;
+
+ udelay ( ATL2_DELAY_10 );
+ }
+
+ if ( !completed )
+ {
+ DBGC ( nic, "FW Restart timed out" );
+ err = -ETIME;
+ goto err_exit;
+ }
+
+ status = ATL_READ_REG ( ATL2_GLB_RST_CTRL2 );
+
+ if ( status & ATL2_RESET_STATUS_BOOT_FAILED_MASK )
+ {
+ err = -EIO;
+ DBGC ( nic, "FW Restart failed" );
+ DBGC ( nic, "status = 0x%x", status );
+ goto err_exit;
+ }
+
+ if ( ATL_READ_REG ( ATL2_HOST_ITR_REQ )
+ & ATL2_FW_HOST_INTERRUPT_REQUEST_READY )
+ {
+ err = -ENOTSUP;
+ DBGC ( nic, "Dynamic FW load not implemented" );
+ goto err_exit;
+ }
+
+ err = atl2_hw_fw_init_ ( nic );
+
+err_exit:
+ return err;
+}
+
+int atl2_hw_start ( struct atl_nic *nic )
+{
+ uint32_t val;
+
+ atl2_hw_read_shared_in_ ( nic, ATL2_LINK_OPTS_IN_OFF, &val, 1 );
+ val = 0x4B00FFE1;
+ atl2_hw_write_shared_in_ ( nic, ATL2_LINK_OPTS_IN_OFF, &val, 1 );
+
+ return atl2_hw_finish_ack_ ( nic, 100000);
+}
+
+int atl2_hw_stop ( struct atl_nic *nic )
+{
+ uint32_t val;
+
+ atl2_hw_read_shared_in_ ( nic, ATL2_LINK_OPTS_IN_OFF, &val, 1 );
+ val = 0;
+ atl2_hw_write_shared_in_ ( nic, ATL2_LINK_OPTS_IN_OFF, &val, 1 );
+
+ return atl2_hw_finish_ack_ ( nic, 100000 );
+}
+
+int atl2_hw_get_link ( struct atl_nic *nic )
+{
+ uint32_t val;
+
+ val = ATL_READ_REG ( ATL2_MIF_SHARED_BUF_OUT + ATL2_LINK_STS_OUT_OFF );
+
+ return ( (val & 0xf) != 0) && ((val & 0xF0) != 0 );
+}
+
+int atl2_hw_get_mac ( struct atl_nic *nic, uint8_t *mac )
+{
+ uint32_t mac_addr[2] = {0};
+
+ atl2_hw_read_shared_in_ ( nic, ATL2_MAC_ADDR_IN_OFF, mac_addr, 2 );
+
+ memcpy ( mac, (uint8_t *)mac_addr, 6 );
+
+ return 0;
+}
+
+struct atl_hw_ops atl2_hw = {
+ .reset = atl2_hw_reset,
+ .start = atl2_hw_start,
+ .stop = atl2_hw_stop,
+ .get_link = atl2_hw_get_link,
+ .get_mac = atl2_hw_get_mac,
+}; \ No newline at end of file
diff --git a/src/drivers/net/marvell/atl2_hw.h b/src/drivers/net/marvell/atl2_hw.h
new file mode 100644
index 00000000..ebd5466e
--- /dev/null
+++ b/src/drivers/net/marvell/atl2_hw.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright(C) 2017-2021 Marvell
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ATL2_HW_H
+#define __ATL2_HW_H
+
+FILE_LICENCE ( BSD2 );
+
+#define ATL2_GLB_RST_CTRL2 0x3040
+#define ATL2_HOST_FINISHED_WRITE 0xE00
+#define ATL2_MCP_BUSY_WRITE 0xE04
+#define ATL2_HOST_ITR_REQ 0xF00
+
+
+#define ATL2_RESET_STATUS_REQ_GSR (1U << 0x0)
+#define ATL2_RESET_STATUS_REQ_HOST_BOOT (1U << 0x8)
+#define ATL2_RESET_STATUS_REQ_MAC_FAST_BOOT (1U << 0xA)
+#define ATL2_RESET_STATUS_REQ_PHY_FAST_BOOT (1U << 0xB)
+
+#define ATL2_RESET_STATUS_HOST_LOAD_COMPLETED (1U << 0x10)
+#define ATL2_RESET_STATUS_REQUIRE_HOST_LOAD (1U << 0x11)
+#define ATL2_RESET_STATUS_BC_STARTED (1U << 0x18)
+#define ATL2_RESET_STATUS_CRASH_DURING_INIT (1U << 0x1B)
+#define ATL2_RESET_STATUS_BC_FAILED (1U << 0x1C)
+#define ATL2_RESET_STATUS_FW_FAILED (1U << 0x1D)
+#define ATL2_RESET_STATUS_FW_SUCCEED (1U << 0x1F)
+
+#define ATL2_RESET_STATUS_BOOT_FAILED_MASK (ATL2_RESET_STATUS_CRASH_DURING_INIT | ATL2_RESET_STATUS_BC_FAILED | ATL2_RESET_STATUS_FW_FAILED)
+#define ATL2_RESET_STATUS_BOOT_COMPLETED_MASK (ATL2_RESET_STATUS_BOOT_FAILED_MASK | ATL2_RESET_STATUS_FW_SUCCEED)
+
+#define ATL2_FW_HOST_INTERRUPT_REQUEST_READY 0x0001
+#define ATL2_FW_HOST_INTERRUPT_MAC_READY 0x0004
+#define ATL2_FW_HOST_INTERRUPT_DATA_HANDLED 0x0100
+#define ATL2_FW_HOST_INTERRUPT_LINK_UP 0x0200
+#define ATL2_FW_HOST_INTERRUPT_LINK_DOWN 0x0400
+#define ATL2_FW_HOST_INTERRUPT_PHY_FAULT 0x0800
+#define ATL2_FW_HOST_INTERRUPT_MAC_FAULT 0x1000
+#define ATL2_FW_HOST_INTERRUPT_TEMPERATURE_WARNING 0x2000
+#define ATL2_FW_HOST_INTERRUPT_HEARTBEAT 0x4000
+
+#define ATL2_FW_LINK_RATE_INVALID 0
+#define ATL2_FW_LINK_RATE_10M 1
+#define ATL2_FW_LINK_RATE_100M 2
+#define ATL2_FW_LINK_RATE_1G 3
+#define ATL2_FW_LINK_RATE_2G5 4
+#define ATL2_FW_LINK_RATE_5G 5
+#define ATL2_FW_LINK_RATE_10G 6
+
+#define ATL2_HOST_MODE_INVALID 0U
+#define ATL2_HOST_MODE_ACTIVE 1U
+#define ATL2_HOST_MODE_SLEEP_PROXY 2U
+#define ATL2_HOST_MODE_LOW_POWER 3U
+#define ATL2_HOST_MODE_SHUTDOWN 4U
+
+#define ATL2_MIF_SHARED_BUF_IN 0x12000
+#define ATL2_MIF_SHARED_BUF_OUT 0x13000
+
+#define ATL2_MTU_IN_OFF 0x0
+#define ATL2_MAC_ADDR_IN_OFF 0x8
+#define ATL2_LINK_CTRL_IN_OFF 0x10
+#define ATL2_LINK_OPTS_IN_OFF 0x18
+
+#define ATL2_FW_OUT_OFF 0x8
+#define ATL2_LINK_STS_OUT_OFF 0x14
+
+#define ATL2_DELAY_10 10
+#define ATL2_DELAY_100 100
+
+#endif \ No newline at end of file
diff --git a/src/drivers/net/marvell/atl_hw.c b/src/drivers/net/marvell/atl_hw.c
new file mode 100644
index 00000000..2dddb718
--- /dev/null
+++ b/src/drivers/net/marvell/atl_hw.c
@@ -0,0 +1,321 @@
+/** @file
+ *
+ * Marvell AQtion family network card driver, hardware-specific functions.
+ *
+ * Copyright(C) 2017-2021 Marvell
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+FILE_LICENCE ( BSD2 );
+
+#include <errno.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <byteswap.h>
+#include <ipxe/pci.h>
+#include "aqc1xx.h"
+#include "atl_hw.h"
+#include <compiler.h>
+
+
+int atl_hw_reset_flb_ ( struct atl_nic *nic )
+{
+ uint32_t val;
+ int k = 0;
+
+ ATL_WRITE_REG ( ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_STALL, ATL_GLB_CTRL2 );
+ mdelay ( ATL_DELAY_50_MNS );
+
+ /* Cleanup SPI */
+ val = ATL_READ_REG ( ATL_GLB_NVR_PROV4 );
+ ATL_WRITE_REG ( val | ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
+
+ ATL_WRITE_REG( (ATL_READ_REG(ATL_GLB_STD_CTRL) &
+ ~ATL_GLB_CTRL_RST_DIS) | ATL_GLB_STD_CTRL_RESET,
+ ATL_GLB_STD_CTRL );
+
+ /* Kickstart MAC */
+ ATL_WRITE_REG ( ATL_GLB_CTRL2_FW_RESET, ATL_GLB_CTRL2 );
+ ATL_WRITE_REG ( ATL_MIF_PWR_GATING_EN_CTRL_RESET,
+ ATL_MIF_PWR_GATING_EN_CTRL );
+
+ ATL_WRITE_REG ( ATL_GEN_PROV9_ENABLE, ATL_GEN_PROV9 );
+
+ /* Reset SPI again because of possible interrupted SPI burst */
+ val = ATL_READ_REG ( ATL_GLB_NVR_PROV4 );
+ ATL_WRITE_REG ( val | ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
+ mdelay ( ATL_DELAY_10_MNS );
+ /* Clear SPI reset state */
+ ATL_WRITE_REG ( val & ~ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
+
+ /* MAC Kickstart */
+ ATL_WRITE_REG ( ATL_GLB_CTRL2_MAC_KICK_START, ATL_GLB_CTRL2 );
+
+ for (k = 0; k < 1000; k++) {
+ uint32_t flb_status = ATL_READ_REG ( ATL_MPI_DAISY_CHAIN_STS );
+
+ flb_status = flb_status & FLB_LOAD_STS;
+ if ( flb_status )
+ break;
+ mdelay ( ATL_DELAY_10_MNS );
+ }
+ if ( k == 1000 ) {
+ DBGC (nic, "MAC kickstart failed\n" );
+ return -EIO;
+ }
+
+ /* FW reset */
+ ATL_WRITE_REG ( ATL_GLB_CTRL2_FW_RESET, ATL_GLB_CTRL2 );
+ mdelay ( ATL_DELAY_50_MNS );
+
+ ATL_WRITE_REG ( ATL_GBL_MCP_SEM1_RELEASE, ATL_GLB_MCP_SEM1 );
+
+ /* Global software reset*/
+ ATL_WRITE_REG ( ATL_READ_REG ( ATL_RX_CTRL ) &
+ ~ATL_RX_CTRL_RST_DIS, ATL_RX_CTRL );
+ ATL_WRITE_REG ( ATL_READ_REG ( ATL_TX_CTRL ) &
+ ~ATL_TX_CTRL_RST_DIS, ATL_TX_CTRL );
+
+ ATL_WRITE_REG ( ATL_READ_REG ( ATL_MAC_PHY_CTRL ) &
+ ~ATL_MAC_PHY_CTRL_RST_DIS, ATL_MAC_PHY_CTRL );
+
+ ATL_WRITE_REG ( ( ATL_READ_REG ( ATL_GLB_STD_CTRL ) &
+ ~ATL_GLB_CTRL_RST_DIS) | ATL_GLB_STD_CTRL_RESET,
+ ATL_GLB_STD_CTRL );
+
+ for (k = 0; k < 1000; k++) {
+ u32 fw_state = ATL_READ_REG ( ATL_FW_VER );
+
+ if ( fw_state )
+ break;
+ mdelay ( ATL_DELAY_10_MNS );
+ }
+ if ( k == 1000 ) {
+ DBGC ( nic, "FW kickstart failed\n" );
+ return -EIO;
+ }
+ /* Old FW requires fixed delay after init */
+ mdelay ( ATL_DELAY_15_MNS );
+
+ return 0;
+}
+
+int atl_hw_reset_rbl_ ( struct atl_nic *nic )
+{
+ uint32_t val, rbl_status;
+ int k;
+
+ ATL_WRITE_REG ( ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_STALL, ATL_GLB_CTRL2 );
+ ATL_WRITE_REG ( ATL_GBL_MCP_SEM1_RELEASE, ATL_GLB_MCP_SEM1 );
+ ATL_WRITE_REG ( ATL_MIF_PWR_GATING_EN_CTRL_RESET,
+ ATL_MIF_PWR_GATING_EN_CTRL );
+
+ /* Alter RBL status */
+ ATL_WRITE_REG ( POISON_SIGN, ATL_MPI_BOOT_EXIT_CODE );
+
+ /* Cleanup SPI */
+ val = ATL_READ_REG ( ATL_GLB_NVR_PROV4 );
+ ATL_WRITE_REG ( val | ATL_GBL_NVR_PROV4_RESET, ATL_GLB_NVR_PROV4 );
+
+ /* Global software reset*/
+ ATL_WRITE_REG ( ATL_READ_REG(ATL_RX_CTRL) & ~ATL_RX_CTRL_RST_DIS,
+ ATL_RX_CTRL );
+ ATL_WRITE_REG ( ATL_READ_REG(ATL_TX_CTRL) & ~ATL_TX_CTRL_RST_DIS,
+ ATL_TX_CTRL );
+ ATL_WRITE_REG ( ATL_READ_REG(ATL_MAC_PHY_CTRL) &
+ ~ATL_MAC_PHY_CTRL_RST_DIS, ATL_MAC_PHY_CTRL );
+
+ ATL_WRITE_REG ( (ATL_READ_REG(ATL_GLB_STD_CTRL) &
+ ~ATL_GLB_CTRL_RST_DIS) | ATL_GLB_STD_CTRL_RESET,
+ ATL_GLB_STD_CTRL );
+
+ ATL_WRITE_REG ( ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_NORMAL, ATL_GLB_CTRL2 );
+
+ /* Wait for RBL boot */
+ for ( k = 0; k < 1000; k++ ) {
+ rbl_status = ATL_READ_REG ( ATL_MPI_BOOT_EXIT_CODE ) & 0xFFFF;
+ if ( rbl_status && rbl_status != POISON_SIGN )
+ break;
+ mdelay ( ATL_DELAY_10_MNS );
+ }
+ if ( !rbl_status || rbl_status == POISON_SIGN ) {
+ DBGC ( nic, "RBL Restart failed\n" );
+ return -EIO;
+ }
+
+ if ( rbl_status == FW_NOT_SUPPORT )
+ return -ENOTSUP;
+
+ for ( k = 0; k < 1000; k++ ) {
+ u32 fw_state = ATL_READ_REG ( ATL_FW_VER );
+
+ if ( fw_state )
+ break;
+ mdelay ( ATL_DELAY_10_MNS );
+ }
+ if ( k == 1000 ) {
+ DBGC ( nic, "FW kickstart failed\n" );
+ return -EIO;
+ }
+ /* Old FW requires fixed delay after init */
+ mdelay ( ATL_DELAY_15_MNS );
+
+ return 0;
+}
+
+int atl_hw_reset ( struct atl_nic *nic )
+{
+ uint32_t boot_exit_code = 0;
+ uint32_t k;
+ int rbl_enabled;
+ uint32_t fw_ver;
+ uint32_t sem_timeout;
+
+ for ( k = 0; k < 1000; ++k ) {
+ uint32_t flb_status = ATL_READ_REG ( ATL_MPI_DAISY_CHAIN_STS );
+ boot_exit_code = ATL_READ_REG ( ATL_MPI_BOOT_EXIT_CODE );
+ if ( flb_status != ATL_MPI_DAISY_CHAIN_STS_ERROR_STATUS ||
+ boot_exit_code != 0 )
+ break;
+ }
+
+ if ( k == 1000 ) {
+ DBGC ( nic, "Neither RBL nor FLB firmware started\n" );
+ return -ENOTSUP;
+ }
+
+ rbl_enabled = (boot_exit_code != 0);
+
+ fw_ver = ATL_READ_REG ( ATL_FW_VER );
+ if ( ((fw_ver >> 24) & 0xFF) >= 4 ) {
+ sem_timeout = ATL_READ_REG ( ATL_SEM_TIMEOUT );
+ if ( sem_timeout > ATL_SEM_MAX_TIMEOUT )
+ sem_timeout = ATL_SEM_MAX_TIMEOUT;
+
+ for ( k = 0; k < sem_timeout; ++k ) {
+ if ( ATL_READ_REG ( ATL_GLB_MCP_SEM4) )
+ break;
+
+ mdelay (ATL_DELAY_1_MNS);
+ }
+ for ( k = 0; k < sem_timeout; ++k ) {
+ if (ATL_READ_REG ( ATL_GLB_MCP_SEM5) )
+ break;
+
+ mdelay ( ATL_DELAY_1_MNS );
+ }
+ }
+
+
+ if ( rbl_enabled )
+ return atl_hw_reset_rbl_ ( nic );
+ else
+ return atl_hw_reset_flb_ ( nic );
+}
+
+int atl_hw_start ( struct atl_nic *nic )
+{
+ ATL_WRITE_REG ( ATL_LINK_ADV_AUTONEG, ATL_LINK_ADV );
+ return 0;
+}
+
+int atl_hw_stop ( struct atl_nic *nic )
+{
+ ATL_WRITE_REG ( ATL_SHUT_LINK, ATL_LINK_ADV );
+ return 0;
+}
+
+int atl_hw_get_link ( struct atl_nic *nic )
+{
+ return ( ATL_READ_REG ( ATL_LINK_ST) & ATL_LINK_ADV_AUTONEG ) != 0;
+}
+
+int atl_hw_read_mem ( struct atl_nic *nic, uint32_t addr, uint32_t *buffer,
+ uint32_t size )
+{
+ uint32_t i;
+
+ for ( i = 0; i < 100; ++i ) {
+ if ( ATL_READ_REG( ATL_SEM_RAM) )
+ break;
+ mdelay ( ATL_DELAY_1_MNS );
+ }
+ if ( i == 100 ) {
+ DBGC (nic, "Semaphore Register not set\n" );
+ return -EIO;
+ }
+
+ ATL_WRITE_REG ( addr, ATL_MBOX_CTRL3 );
+
+ for ( i = 0; i < size; ++i, addr += 4 ) {
+ uint32_t j;
+
+ ATL_WRITE_REG ( ATL_MBOX_CTRL1_START_MBOX_OPT, ATL_MBOX_CTRL1 );
+ for ( j = 0; j < 10000; ++j ) {
+ if ( ATL_READ_REG (ATL_MBOX_CTRL3 ) != addr )
+ break;
+ udelay ( ATL_DELAY_10_MNS );
+ }
+ if ( j == 10000 ) {
+ DBGC (nic, "Reading from CTRL3 Register Failed\n" );
+ return -EIO;
+ }
+
+ buffer[i] = ATL_READ_REG ( ATL_MBOX_CTRL5 );
+ }
+
+ ATL_WRITE_REG( ATL_SEM_RAM_RESET, ATL_SEM_RAM );
+
+ return 0;
+}
+
+int atl_hw_get_mac ( struct atl_nic *nic, uint8_t *mac )
+{
+ uint32_t mac_addr[2] = {0};
+ int err = 0;
+ uint32_t efuse_addr = ATL_READ_REG ( ATL_GLB_MCP_SP26 );
+
+ if ( efuse_addr != 0) {
+ uint32_t mac_efuse_addr = efuse_addr + 40 * sizeof(uint32_t);
+ err = atl_hw_read_mem ( nic, mac_efuse_addr, mac_addr, 2 );
+ if ( err != 0 )
+ return err;
+
+ mac_addr[0] = cpu_to_be32 ( mac_addr[0] );
+ mac_addr[1] = cpu_to_be32 ( mac_addr[1] );
+
+ memcpy ( mac, (uint8_t *)mac_addr, ATL_MAC_ADDRESS_SIZE );
+ }
+ return 0;
+}
+
+struct atl_hw_ops atl_hw = {
+ .reset = atl_hw_reset,
+ .start = atl_hw_start,
+ .stop = atl_hw_stop,
+ .get_link = atl_hw_get_link,
+ .get_mac = atl_hw_get_mac,
+}; \ No newline at end of file
diff --git a/src/drivers/net/marvell/atl_hw.h b/src/drivers/net/marvell/atl_hw.h
new file mode 100644
index 00000000..0a20fbfc
--- /dev/null
+++ b/src/drivers/net/marvell/atl_hw.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright(C) 2017-2021 Marvell
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO,THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef __ATL_HW_H
+#define __ATL_HW_H
+
+FILE_LICENCE ( BSD2 );
+
+#define ATL_GLB_STD_CTRL 0x0
+#define ATL_GLB_CTRL_RST_DIS 0x4000
+#define ATL_FW_VER 0x18
+
+#define ATL_MPI_DAISY_CHAIN_STS 0x704
+#define ATL_MPI_RX_DAISY_CHAIN_DATA 0x04000000
+#define ATL_MPI_RX_DAISY_CHAIN_SOF 0x02000000
+#define FLB_LOAD_STS 0x10
+
+#define ATL_MPI_BOOT_EXIT_CODE 0x388
+
+#define ATL_SEM_TIMEOUT 0x348
+#define ATL_SEM_MAX_TIMEOUT 3000
+
+#define ATL_GLB_CTRL2 0x404
+#define ATL_GLB_MCP_SEM1 0x3A0
+#define ATL_GBL_MCP_SEM1_RELEASE 0x1
+
+#define ATL_GLB_MCP_SEM4 0x3AC
+#define ATL_GLB_MCP_SEM5 0x3B0
+#define ATL_GLB_MCP_SP26 0x364
+#define ATL_MIF_PWR_GATING_EN_CTRL 0x32A8
+
+#define ATL_GLB_NVR_PROV4 0x53C
+#define ATL_GBL_NVR_PROV4_RESET 0x10
+
+
+#define ATL_GEN_PROV9 0x520
+
+#define ATL_MAC_PHY_CTRL 0x00004000U
+#define ATL_MAC_PHY_CTRL_RST_DIS 0x20000000U
+
+#define ATL_MIF_PWR_GATING_EN_CTRL_RESET 0x0
+#define ATL_GEN_PROV9_ENABLE 0x1
+#define ATL_GLB_CTRL2_MAC_KICK_START 0x180e0
+#define ATL_GLB_CTRL2_FW_RESET 0x80e0
+#define ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_STALL 0x40e1
+#define ATL_GLB_CTRL2_MBOX_ERR_UP_RUN_NORMAL 0x40e0
+#define ATL_GLB_STD_CTRL_RESET 0x8000
+#define ATL_MPI_DAISY_CHAIN_STS_ERROR_STATUS 0x06000000
+
+#define ATL_DELAY_1_MNS 1
+#define ATL_DELAY_10_MNS 10
+#define ATL_DELAY_15_MNS 15
+#define ATL_DELAY_50_MNS 50
+
+#define ATL_MAC_ADDRESS_SIZE 6
+#define POISON_SIGN 0xDEAD
+#define FW_NOT_SUPPORT 0xF1A7
+
+#endif
diff --git a/src/drivers/net/ns8390.c b/src/drivers/net/ns8390.c
index 0ffc6216..8e8d8500 100644
--- a/src/drivers/net/ns8390.c
+++ b/src/drivers/net/ns8390.c
@@ -1006,17 +1006,17 @@ ISA_ROM("ne","NE1000/2000 and clones");
#ifdef INCLUDE_NS8390
static struct pci_device_id nepci_nics[] = {
/* A few NE2000 PCI clones, list not exhaustive */
-PCI_ROM(0x10ec, 0x8029, "rtl8029", "Realtek 8029", 0),
-PCI_ROM(0x1186, 0x0300, "dlink-528", "D-Link DE-528", 0),
PCI_ROM(0x1050, 0x0940, "winbond940", "Winbond NE2000-PCI", 0), /* Winbond 86C940 / 89C940 */
PCI_ROM(0x1050, 0x5a5a, "winbond940f", "Winbond W89c940F", 0), /* Winbond 89C940F */
+PCI_ROM(0x10bd, 0x0e34, "surecom-ne34", "Surecom NE34", 0),
+PCI_ROM(0x10ec, 0x8029, "rtl8029", "Realtek 8029", 0),
+PCI_ROM(0x1106, 0x0926, "via86c926", "Via 86c926", 0),
+PCI_ROM(0x1186, 0x0300, "dlink-528", "D-Link DE-528", 0),
PCI_ROM(0x11f6, 0x1401, "compexrl2000", "Compex ReadyLink 2000", 0),
-PCI_ROM(0x8e2e, 0x3000, "ktiet32p2", "KTI ET32P2", 0),
-PCI_ROM(0x4a14, 0x5000, "nv5000sc", "NetVin NV5000SC", 0),
PCI_ROM(0x12c3, 0x0058, "holtek80232", "Holtek HT80232", 0),
PCI_ROM(0x12c3, 0x5598, "holtek80229", "Holtek HT80229", 0),
-PCI_ROM(0x10bd, 0x0e34, "surecom-ne34", "Surecom NE34", 0),
-PCI_ROM(0x1106, 0x0926, "via86c926", "Via 86c926", 0),
+PCI_ROM(0x4a14, 0x5000, "nv5000sc", "NetVin NV5000SC", 0),
+PCI_ROM(0x8e2e, 0x3000, "ktiet32p2", "KTI ET32P2", 0),
};
PCI_DRIVER ( nepci_driver, nepci_nics, PCI_NO_CLASS );
diff --git a/src/drivers/net/pcnet32.c b/src/drivers/net/pcnet32.c
index 7da884e5..a9286d6a 100644
--- a/src/drivers/net/pcnet32.c
+++ b/src/drivers/net/pcnet32.c
@@ -1149,8 +1149,8 @@ pcnet32_remove ( struct pci_device *pdev )
static struct pci_device_id pcnet32_nics[] = {
PCI_ROM(0x1022, 0x2000, "pcnet32", "AMD PCnet/PCI", 0),
- PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III", 0),
PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD PCnet/HomePNA", 0),
+ PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III", 0),
};
struct pci_driver pcnet32_driver __pci_driver = {
diff --git a/src/drivers/net/prism2_plx.c b/src/drivers/net/prism2_plx.c
index a73b0e08..770cf328 100644
--- a/src/drivers/net/prism2_plx.c
+++ b/src/drivers/net/prism2_plx.c
@@ -104,9 +104,10 @@ static void prism2_plx_disable ( struct nic *nic ) {
}
static struct pci_device_id prism2_plx_nics[] = {
-PCI_ROM(0x1385, 0x4100, "ma301", "Netgear MA301", 0),
PCI_ROM(0x10b7, 0x7770, "3c-airconnect", "3Com AirConnect", 0),
PCI_ROM(0x111a, 0x1023, "ss1023", "Siemens SpeedStream SS1023", 0),
+PCI_ROM(0x126c, 0x8030, "emobility", "Nortel emobility", 0),
+PCI_ROM(0x1385, 0x4100, "ma301", "Netgear MA301", 0),
PCI_ROM(0x15e8, 0x0130, "correga", "Correga", 0),
PCI_ROM(0x1638, 0x1100, "smc2602w", "SMC EZConnect SMC2602W", 0), /* or Eumitcom PCI WL11000, Addtron AWA-100 */
PCI_ROM(0x16ab, 0x1100, "gl24110p", "Global Sun Tech GL24110P", 0),
@@ -114,7 +115,6 @@ PCI_ROM(0x16ab, 0x1101, "16ab-1101", "Unknown", 0),
PCI_ROM(0x16ab, 0x1102, "wdt11", "Linksys WDT11", 0),
PCI_ROM(0x16ec, 0x3685, "usr2415", "USR 2415", 0),
PCI_ROM(0xec80, 0xec00, "f5d6000", "Belkin F5D6000", 0),
-PCI_ROM(0x126c, 0x8030, "emobility", "Nortel emobility", 0),
};
PCI_DRIVER ( prism2_plx_driver, prism2_plx_nics, PCI_NO_CLASS );
diff --git a/src/drivers/net/rhine.c b/src/drivers/net/rhine.c
index f4d3a258..fa0876ad 100644
--- a/src/drivers/net/rhine.c
+++ b/src/drivers/net/rhine.c
@@ -775,10 +775,10 @@ static void rhine_remove ( struct pci_device *pci ) {
/** Rhine PCI device IDs */
static struct pci_device_id rhine_nics[] = {
- PCI_ROM ( 0x1106, 0x3065, "dlink-530tx", "VIA VT6102", 0 ),
- PCI_ROM ( 0x1106, 0x3106, "vt6105", "VIA VT6105", 0 ),
PCI_ROM ( 0x1106, 0x3043, "dlink-530tx-old", "VIA VT3043", 0 ),
PCI_ROM ( 0x1106, 0x3053, "vt6105m", "VIA VT6105M", 0 ),
+ PCI_ROM ( 0x1106, 0x3065, "dlink-530tx", "VIA VT6102", 0 ),
+ PCI_ROM ( 0x1106, 0x3106, "vt6105", "VIA VT6105", 0 ),
PCI_ROM ( 0x1106, 0x6100, "via-rhine-old", "VIA 86C100A", 0 )
};
diff --git a/src/drivers/net/rtl818x/rtl8180.c b/src/drivers/net/rtl818x/rtl8180.c
index 5f97480f..b3f68541 100644
--- a/src/drivers/net/rtl818x/rtl8180.c
+++ b/src/drivers/net/rtl818x/rtl8180.c
@@ -7,9 +7,9 @@ FILE_LICENCE(GPL2_OR_LATER);
static struct pci_device_id rtl8180_nics[] = {
PCI_ROM(0x10ec, 0x8180, "rtl8180", "Realtek 8180", 0),
+ PCI_ROM(0x1186, 0x3300, "dwl510", "D-Link DWL-510", 0),
PCI_ROM(0x1799, 0x6001, "f5d6001", "Belkin F5D6001", 0),
PCI_ROM(0x1799, 0x6020, "f5d6020", "Belkin F5D6020", 0),
- PCI_ROM(0x1186, 0x3300, "dwl510", "D-Link DWL-510", 0),
};
struct pci_driver rtl8180_driver __pci_driver = {
diff --git a/src/drivers/net/sky2.c b/src/drivers/net/sky2.c
index 26396585..4f8ec3e4 100644
--- a/src/drivers/net/sky2.c
+++ b/src/drivers/net/sky2.c
@@ -81,8 +81,8 @@ FILE_LICENCE ( GPL2_ONLY );
static struct pci_device_id sky2_id_table[] = {
PCI_ROM(0x1148, 0x9000, "sk9sxx", "Syskonnect SK-9Sxx", 0),
PCI_ROM(0x1148, 0x9e00, "sk9exx", "Syskonnect SK-9Exx", 0),
- PCI_ROM(0x1186, 0x4b00, "dge560t", "D-Link DGE-560T", 0),
PCI_ROM(0x1186, 0x4001, "dge550sx", "D-Link DGE-550SX", 0),
+ PCI_ROM(0x1186, 0x4b00, "dge560t", "D-Link DGE-560T", 0),
PCI_ROM(0x1186, 0x4b02, "dge560sx", "D-Link DGE-560SX", 0),
PCI_ROM(0x1186, 0x4b03, "dge550t", "D-Link DGE-550T", 0),
PCI_ROM(0x11ab, 0x4340, "m88e8021", "Marvell 88E8021", 0),
diff --git a/src/drivers/net/sundance.c b/src/drivers/net/sundance.c
index 9127fa2c..8eb09b98 100644
--- a/src/drivers/net/sundance.c
+++ b/src/drivers/net/sundance.c
@@ -880,9 +880,9 @@ static void set_rx_mode(struct nic *nic __unused)
}
static struct pci_device_id sundance_nics[] = {
- PCI_ROM(0x13f0, 0x0201, "sundance", "ST201 Sundance 'Alta' based Adaptor", 0),
PCI_ROM(0x1186, 0x1002, "dfe530txs", "D-Link DFE530TXS (Sundance ST201 Alta)", 0),
PCI_ROM(0x13f0, 0x0200, "ip100a", "IC+ IP100A", 0),
+ PCI_ROM(0x13f0, 0x0201, "sundance", "ST201 Sundance 'Alta' based Adaptor", 0),
};
PCI_DRIVER ( sundance_driver, sundance_nics, PCI_NO_CLASS );
diff --git a/src/drivers/net/tg3/tg3.c b/src/drivers/net/tg3/tg3.c
index 559c2d63..05af22d6 100644
--- a/src/drivers/net/tg3/tg3.c
+++ b/src/drivers/net/tg3/tg3.c
@@ -856,88 +856,88 @@ static void tg3_remove_one(struct pci_device *pci)
}
static struct pci_device_id tg3_nics[] = {
+ PCI_ROM(0x106b, 0x1645, "106b-1645", "106b-1645", 0),
+ PCI_ROM(0x1148, 0x4400, "1148-4400", "1148-4400", 0),
+ PCI_ROM(0x1148, 0x4500, "1148-4500", "1148-4500", 0),
+ PCI_ROM(0x14e4, 0x1600, "14e4-1600", "14e4-1600", 0),
+ PCI_ROM(0x14e4, 0x1601, "14e4-1601", "14e4-1601", 0),
PCI_ROM(0x14e4, 0x1644, "14e4-1644", "14e4-1644", 0),
PCI_ROM(0x14e4, 0x1645, "14e4-1645", "14e4-1645", 0),
PCI_ROM(0x14e4, 0x1646, "14e4-1646", "14e4-1646", 0),
PCI_ROM(0x14e4, 0x1647, "14e4-1647", "14e4-1647", 0),
PCI_ROM(0x14e4, 0x1648, "14e4-1648", "14e4-1648", 0),
+ PCI_ROM(0x14e4, 0x1649, "14e4-1649", "14e4-1649", 0),
PCI_ROM(0x14e4, 0x164d, "14e4-164d", "14e4-164d", 0),
PCI_ROM(0x14e4, 0x1653, "14e4-1653", "14e4-1653", 0),
PCI_ROM(0x14e4, 0x1654, "14e4-1654", "14e4-1654", 0),
+ PCI_ROM(0x14e4, 0x1655, "14e4-1655", "14e4-1655", 0),
+ PCI_ROM(0x14e4, 0x1656, "14e4-1656", "14e4-1656", 0),
+ PCI_ROM(0x14e4, 0x1657, "14e4-1657", "14e4-1657", 0),
+ PCI_ROM(0x14e4, 0x1659, "14e4-1659", "14e4-1659", 0),
+ PCI_ROM(0x14e4, 0x165a, "14e4-165a", "14e4-165a", 0),
+ PCI_ROM(0x14e4, 0x165b, "14e4-165b", "14e4-165b", 0),
PCI_ROM(0x14e4, 0x165d, "14e4-165d", "14e4-165d", 0),
PCI_ROM(0x14e4, 0x165e, "14e4-165e", "14e4-165e", 0),
- PCI_ROM(0x14e4, 0x16a6, "14e4-16a6", "14e4-16a6", 0),
- PCI_ROM(0x14e4, 0x16a7, "14e4-16a7", "14e4-16a7", 0),
- PCI_ROM(0x14e4, 0x16a8, "14e4-16a8", "14e4-16a8", 0),
- PCI_ROM(0x14e4, 0x16c6, "14e4-16c6", "14e4-16c6", 0),
- PCI_ROM(0x14e4, 0x16c7, "14e4-16c7", "14e4-16c7", 0),
- PCI_ROM(0x14e4, 0x1696, "14e4-1696", "14e4-1696", 0),
- PCI_ROM(0x14e4, 0x169c, "14e4-169c", "14e4-169c", 0),
- PCI_ROM(0x14e4, 0x169d, "14e4-169d", "14e4-169d", 0),
- PCI_ROM(0x14e4, 0x170d, "14e4-170d", "14e4-170d", 0),
- PCI_ROM(0x14e4, 0x170e, "14e4-170e", "14e4-170e", 0),
- PCI_ROM(0x14e4, 0x1649, "14e4-1649", "14e4-1649", 0),
+ PCI_ROM(0x14e4, 0x165f, "14e4-165f", "14e4-165f", 0),
+ PCI_ROM(0x14e4, 0x1668, "14e4-1668", "14e4-1668", 0),
+ PCI_ROM(0x14e4, 0x1669, "14e4-1669", "14e4-1669", 0),
+ PCI_ROM(0x14e4, 0x166a, "14e4-166a", "14e4-166a", 0),
+ PCI_ROM(0x14e4, 0x166b, "14e4-166b", "14e4-166b", 0),
PCI_ROM(0x14e4, 0x166e, "14e4-166e", "14e4-166e", 0),
- PCI_ROM(0x14e4, 0x1659, "14e4-1659", "14e4-1659", 0),
- PCI_ROM(0x14e4, 0x165a, "14e4-165a", "14e4-165a", 0),
- PCI_ROM(0x14e4, 0x1677, "14e4-1677", "14e4-1677", 0),
- PCI_ROM(0x14e4, 0x167d, "14e4-167d", "14e4-167d", 0),
- PCI_ROM(0x14e4, 0x167e, "14e4-167e", "14e4-167e", 0),
- PCI_ROM(0x14e4, 0x1600, "14e4-1600", "14e4-1600", 0),
- PCI_ROM(0x14e4, 0x1601, "14e4-1601", "14e4-1601", 0),
- PCI_ROM(0x14e4, 0x16f7, "14e4-16f7", "14e4-16f7", 0),
- PCI_ROM(0x14e4, 0x16fd, "14e4-16fd", "14e4-16fd", 0),
- PCI_ROM(0x14e4, 0x16fe, "14e4-16fe", "14e4-16fe", 0),
- PCI_ROM(0x14e4, 0x167a, "14e4-167a", "14e4-167a", 0),
PCI_ROM(0x14e4, 0x1672, "14e4-1672", "14e4-1672", 0),
- PCI_ROM(0x14e4, 0x167b, "14e4-167b", "14e4-167b", 0),
PCI_ROM(0x14e4, 0x1673, "14e4-1673", "14e4-1673", 0),
PCI_ROM(0x14e4, 0x1674, "14e4-1674", "14e4-1674", 0),
- PCI_ROM(0x14e4, 0x169a, "14e4-169a", "14e4-169a", 0),
- PCI_ROM(0x14e4, 0x169b, "14e4-169b", "14e4-169b", 0),
- PCI_ROM(0x14e4, 0x1693, "14e4-1693", "14e4-1693", 0),
- PCI_ROM(0x14e4, 0x167f, "14e4-167f", "14e4-167f", 0),
- PCI_ROM(0x14e4, 0x1668, "14e4-1668", "14e4-1668", 0),
- PCI_ROM(0x14e4, 0x1669, "14e4-1669", "14e4-1669", 0),
+ PCI_ROM(0x14e4, 0x1677, "14e4-1677", "14e4-1677", 0),
PCI_ROM(0x14e4, 0x1678, "14e4-1678", "14e4-1678", 0),
PCI_ROM(0x14e4, 0x1679, "14e4-1679", "14e4-1679", 0),
- PCI_ROM(0x14e4, 0x166a, "14e4-166a", "14e4-166a", 0),
- PCI_ROM(0x14e4, 0x166b, "14e4-166b", "14e4-166b", 0),
- PCI_ROM(0x14e4, 0x16dd, "14e4-16dd", "14e4-16dd", 0),
- PCI_ROM(0x14e4, 0x1712, "14e4-1712", "14e4-1712", 0),
- PCI_ROM(0x14e4, 0x1713, "14e4-1713", "14e4-1713", 0),
- PCI_ROM(0x14e4, 0x1698, "14e4-1698", "14e4-1698", 0),
- PCI_ROM(0x14e4, 0x1684, "14e4-1684", "14e4-1684", 0),
- PCI_ROM(0x14e4, 0x165b, "14e4-165b", "14e4-165b", 0),
+ PCI_ROM(0x14e4, 0x167a, "14e4-167a", "14e4-167a", 0),
+ PCI_ROM(0x14e4, 0x167b, "14e4-167b", "14e4-167b", 0),
+ PCI_ROM(0x14e4, 0x167d, "14e4-167d", "14e4-167d", 0),
+ PCI_ROM(0x14e4, 0x167e, "14e4-167e", "14e4-167e", 0),
+ PCI_ROM(0x14e4, 0x167f, "14e4-167f", "14e4-167f", 0),
+ PCI_ROM(0x14e4, 0x1680, "14e4-1680", "14e4-1680", 0),
PCI_ROM(0x14e4, 0x1681, "14e4-1681", "14e4-1681", 0),
PCI_ROM(0x14e4, 0x1682, "14e4-1682", "14e4-1682", 0),
- PCI_ROM(0x14e4, 0x1680, "14e4-1680", "14e4-1680", 0),
+ PCI_ROM(0x14e4, 0x1684, "14e4-1684", "14e4-1684", 0),
+ PCI_ROM(0x14e4, 0x1686, "14e4-1686", "14e4-1686", 0),
PCI_ROM(0x14e4, 0x1688, "14e4-1688", "14e4-1688", 0),
PCI_ROM(0x14e4, 0x1689, "14e4-1689", "14e4-1689", 0),
- PCI_ROM(0x14e4, 0x1699, "14e4-1699", "14e4-1699", 0),
- PCI_ROM(0x14e4, 0x16a0, "14e4-16a0", "14e4-16a0", 0),
- PCI_ROM(0x14e4, 0x1692, "14e4-1692", "14e4-1692", 0),
PCI_ROM(0x14e4, 0x1690, "14e4-1690", "14e4-1690", 0),
- PCI_ROM(0x14e4, 0x1694, "14e4-1694", "14e4-1694", 0),
PCI_ROM(0x14e4, 0x1691, "14e4-1691", "14e4-1691", 0),
- PCI_ROM(0x14e4, 0x1655, "14e4-1655", "14e4-1655", 0),
- PCI_ROM(0x14e4, 0x1656, "14e4-1656", "14e4-1656", 0),
- PCI_ROM(0x14e4, 0x16b1, "14e4-16b1", "14e4-16b1", 0),
- PCI_ROM(0x14e4, 0x16b5, "14e4-16b5", "14e4-16b5", 0),
+ PCI_ROM(0x14e4, 0x1692, "14e4-1692", "14e4-1692", 0),
+ PCI_ROM(0x14e4, 0x1693, "14e4-1693", "14e4-1693", 0),
+ PCI_ROM(0x14e4, 0x1694, "14e4-1694", "14e4-1694", 0),
+ PCI_ROM(0x14e4, 0x1696, "14e4-1696", "14e4-1696", 0),
+ PCI_ROM(0x14e4, 0x1698, "14e4-1698", "14e4-1698", 0),
+ PCI_ROM(0x14e4, 0x1699, "14e4-1699", "14e4-1699", 0),
+ PCI_ROM(0x14e4, 0x169a, "14e4-169a", "14e4-169a", 0),
+ PCI_ROM(0x14e4, 0x169b, "14e4-169b", "14e4-169b", 0),
+ PCI_ROM(0x14e4, 0x169c, "14e4-169c", "14e4-169c", 0),
+ PCI_ROM(0x14e4, 0x169d, "14e4-169d", "14e4-169d", 0),
+ PCI_ROM(0x14e4, 0x16a0, "14e4-16a0", "14e4-16a0", 0),
+ PCI_ROM(0x14e4, 0x16a6, "14e4-16a6", "14e4-16a6", 0),
+ PCI_ROM(0x14e4, 0x16a7, "14e4-16a7", "14e4-16a7", 0),
+ PCI_ROM(0x14e4, 0x16a8, "14e4-16a8", "14e4-16a8", 0),
PCI_ROM(0x14e4, 0x16b0, "14e4-16b0", "14e4-16b0", 0),
- PCI_ROM(0x14e4, 0x16b4, "14e4-16b4", "14e4-16b4", 0),
+ PCI_ROM(0x14e4, 0x16b1, "14e4-16b1", "14e4-16b1", 0),
PCI_ROM(0x14e4, 0x16b2, "14e4-16b2", "14e4-16b2", 0),
+ PCI_ROM(0x14e4, 0x16b4, "14e4-16b4", "14e4-16b4", 0),
+ PCI_ROM(0x14e4, 0x16b5, "14e4-16b5", "14e4-16b5", 0),
PCI_ROM(0x14e4, 0x16b6, "14e4-16b6", "14e4-16b6", 0),
- PCI_ROM(0x14e4, 0x1657, "14e4-1657", "14e4-1657", 0),
- PCI_ROM(0x14e4, 0x165f, "14e4-165f", "14e4-165f", 0),
- PCI_ROM(0x14e4, 0x1686, "14e4-1686", "14e4-1686", 0),
- PCI_ROM(0x1148, 0x4400, "1148-4400", "1148-4400", 0),
- PCI_ROM(0x1148, 0x4500, "1148-4500", "1148-4500", 0),
+ PCI_ROM(0x14e4, 0x16c6, "14e4-16c6", "14e4-16c6", 0),
+ PCI_ROM(0x14e4, 0x16c7, "14e4-16c7", "14e4-16c7", 0),
+ PCI_ROM(0x14e4, 0x16dd, "14e4-16dd", "14e4-16dd", 0),
+ PCI_ROM(0x14e4, 0x16f7, "14e4-16f7", "14e4-16f7", 0),
+ PCI_ROM(0x14e4, 0x16fd, "14e4-16fd", "14e4-16fd", 0),
+ PCI_ROM(0x14e4, 0x16fe, "14e4-16fe", "14e4-16fe", 0),
+ PCI_ROM(0x14e4, 0x170d, "14e4-170d", "14e4-170d", 0),
+ PCI_ROM(0x14e4, 0x170e, "14e4-170e", "14e4-170e", 0),
+ PCI_ROM(0x14e4, 0x1712, "14e4-1712", "14e4-1712", 0),
+ PCI_ROM(0x14e4, 0x1713, "14e4-1713", "14e4-1713", 0),
PCI_ROM(0x173b, 0x03e8, "173b-03e8", "173b-03e8", 0),
PCI_ROM(0x173b, 0x03e9, "173b-03e9", "173b-03e9", 0),
- PCI_ROM(0x173b, 0x03eb, "173b-03eb", "173b-03eb", 0),
PCI_ROM(0x173b, 0x03ea, "173b-03ea", "173b-03ea", 0),
- PCI_ROM(0x106b, 0x1645, "106b-1645", "106b-1645", 0),
+ PCI_ROM(0x173b, 0x03eb, "173b-03eb", "173b-03eb", 0),
};
struct pci_driver tg3_pci_driver __pci_driver = {
diff --git a/src/drivers/net/tlan.c b/src/drivers/net/tlan.c
index 0e85b35b..93533b43 100644
--- a/src/drivers/net/tlan.c
+++ b/src/drivers/net/tlan.c
@@ -1697,19 +1697,19 @@ void TLan_PhyMonitor(struct net_device *dev)
#endif /* MONITOR */
static struct pci_device_id tlan_nics[] = {
- PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0),
+ PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0),
- PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
- PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
- PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0),
+ PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0),
- PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
+ PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
+ PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
+ PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
+ PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0),
+ PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0),
- PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
- PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
};
PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
diff --git a/src/drivers/net/tulip.c b/src/drivers/net/tulip.c
index e4e6ffa8..fddebfe5 100644
--- a/src/drivers/net/tulip.c
+++ b/src/drivers/net/tulip.c
@@ -1921,31 +1921,30 @@ PCI_ROM(0x1011, 0x0002, "dc21040", "Digital Tulip", 0),
PCI_ROM(0x1011, 0x0009, "ds21140", "Digital Tulip Fast", 0),
PCI_ROM(0x1011, 0x0014, "dc21041", "Digital Tulip+", 0),
PCI_ROM(0x1011, 0x0019, "ds21142", "Digital Tulip 21142", 0),
+PCI_ROM(0x104a, 0x0981, "tulip-0981", "Tulip 0x104a 0x0981", 0),
+PCI_ROM(0x104a, 0x2774, "SGThomson-STE10100A", "Tulip 0x104a 0x2774", 0), /*Modified by Ramesh Chander*/
PCI_ROM(0x10b7, 0x9300, "3csoho100b-tx","3ComSOHO100B-TX", 0),
PCI_ROM(0x10b9, 0x5261, "ali1563", "ALi 1563 integrated ethernet", 0),
PCI_ROM(0x10d9, 0x0512, "mx98713", "Macronix MX987x3", 0),
PCI_ROM(0x10d9, 0x0531, "mx98715", "Macronix MX987x5", 0),
+PCI_ROM(0x1113, 0x1216, "an983", "ADMTek AN983 Comet", 0),
PCI_ROM(0x1113, 0x1217, "mxic-98715", "Macronix MX987x5", 0),
-PCI_ROM(0x11ad, 0xc115, "lc82c115", "LinkSys LNE100TX", 0),
+PCI_ROM(0x1113, 0x9511, "tulip-9511", "Tulip 0x1113 0x9511", 0),
+PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip", 0),
+PCI_ROM(0x1186, 0x1561, "tulip-1561", "Tulip 0x1186 0x1561", 0),
PCI_ROM(0x11ad, 0x0002, "82c168", "Netgear FA310TX", 0),
+PCI_ROM(0x11ad, 0xc115, "lc82c115", "LinkSys LNE100TX", 0),
+PCI_ROM(0x11f6, 0x9881, "rl100tx", "Compex RL100-TX", 0),
+PCI_ROM(0x1259, 0xa120, "tulip-a120", "Tulip 0x1259 0xa120", 0),
+PCI_ROM(0x125b, 0x1400, "ax88140", "ASIX AX88140", 0),
+PCI_ROM(0x1282, 0x9009, "dm9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9100, "dm9100", "Davicom 9100", 0),
PCI_ROM(0x1282, 0x9102, "dm9102", "Davicom 9102", 0),
-PCI_ROM(0x1282, 0x9009, "dm9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9132, "dm9132", "Davicom 9132", 0),
-PCI_ROM(0x1317, 0x0985, "centaur-p", "ADMtek Centaur-P", 0),
PCI_ROM(0x1317, 0x0981, "an981", "ADMtek AN981 Comet", 0), /* ADMTek Centaur-P (stmicro) */
-PCI_ROM(0x1113, 0x1216, "an983", "ADMTek AN983 Comet", 0),
-PCI_ROM(0x1317, 0x9511, "an983b", "ADMTek Comet 983b", 0),
+PCI_ROM(0x1317, 0x0985, "centaur-p", "ADMtek Centaur-P", 0),
PCI_ROM(0x1317, 0x1985, "centaur-c", "ADMTek Centaur-C", 0),
-PCI_ROM(0x8086, 0x0039, "intel21145", "Intel Tulip", 0),
-PCI_ROM(0x125b, 0x1400, "ax88140", "ASIX AX88140", 0),
-PCI_ROM(0x11f6, 0x9881, "rl100tx", "Compex RL100-TX", 0),
-PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip", 0),
-PCI_ROM(0x104a, 0x0981, "tulip-0981", "Tulip 0x104a 0x0981", 0),
-PCI_ROM(0x104a, 0x2774, "SGThomson-STE10100A", "Tulip 0x104a 0x2774", 0), /*Modified by Ramesh Chander*/
-PCI_ROM(0x1113, 0x9511, "tulip-9511", "Tulip 0x1113 0x9511", 0),
-PCI_ROM(0x1186, 0x1561, "tulip-1561", "Tulip 0x1186 0x1561", 0),
-PCI_ROM(0x1259, 0xa120, "tulip-a120", "Tulip 0x1259 0xa120", 0),
+PCI_ROM(0x1317, 0x9511, "an983b", "ADMTek Comet 983b", 0),
PCI_ROM(0x13d1, 0xab02, "tulip-ab02", "Tulip 0x13d1 0xab02", 0),
PCI_ROM(0x13d1, 0xab03, "tulip-ab03", "Tulip 0x13d1 0xab03", 0),
PCI_ROM(0x13d1, 0xab08, "tulip-ab08", "Tulip 0x13d1 0xab08", 0),
@@ -1953,6 +1952,7 @@ PCI_ROM(0x14f1, 0x1803, "lanfinity", "Conexant LANfinity", 0),
PCI_ROM(0x1626, 0x8410, "tulip-8410", "Tulip 0x1626 0x8410", 0),
PCI_ROM(0x1737, 0xab08, "tulip-1737-ab08","Tulip 0x1737 0xab08", 0),
PCI_ROM(0x1737, 0xab09, "tulip-ab09", "Tulip 0x1737 0xab09", 0),
+PCI_ROM(0x8086, 0x0039, "intel21145", "Intel Tulip", 0),
};
PCI_DRIVER ( tulip_driver, tulip_nics, PCI_NO_CLASS );